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Method for forming via contact hole in a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
출원번호 US-0943891 (1997-10-03)
발명자 / 주소
  • Solis Ramiro
출원인 / 주소
  • Vlsi Technology, Inc.
대리인 / 주소
    Burns, Doane, Swecker & Mathis LLP
인용정보 피인용 횟수 : 24  인용 특허 : 15

초록

A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is pr

대표청구항

[ What is claimed is:] [1.] A method of forming a via contact hole in a semiconductor device that comprises the steps of:forming a metal layer on a wafer;forming a dielectric layer on said metal layer;forming a photoresist pattern after a photoresist layer is coated on said dielectric layer;forming

이 특허에 인용된 특허 (15)

  1. Yano ; Kozo ; Inami ; Yasuhiko ; Hamada ; Hiroshi ; Uede ; Hisashi, Electrochromic display device manufacture method.
  2. Bailey Wayne E. (Garland TX) Baker James C. (Coppell TX), Fabrication method for digital micro-mirror devices using low temperature CVD.
  3. Klepner Stephen P. (Wappingers Falls NY), Groundplane post-etch anodization.
  4. Bohannon Brynne K. (Sachse TX) Syverson Daniel J. (Chaska MN), Metal selective polymer removal.
  5. Walker William K. (Plano TX), Method for dry etching of post-processing interconnection metal on hybrid integrated circuits.
  6. Park Sung-Kil (Kyoungki KRX) Kim Dong-Sauk (Seoul KRX) Yoon Yong-Hyeock (Seoul KRX), Method for forming a via contact hole of a semiconductor device.
  7. Sutcliffe Gary R. (Kensington CT) Conrod Jay B. (Cheshire CT), Method for manufacture of printed circuit boards.
  8. Cleeves James M. (Redwood City CA), Planar antifuse and method of fabrication.
  9. Thomas Michael E. (Cupertino CA) Brown Robert L. (Palo Alto CA), Process for forming vias on integrated circuits.
  10. Yang Ming-Tzung (Hsin-chu TWX) Hong Gary (Hsin-chu TWX), Process for post metal coding of a ROM, by gate etch.
  11. Fujimura Shuzo (Tokyo JPX) Shinagawa Keisuke (Kawasaki JPX) Hikazutani Kenichi (Kuwana JPX), Processing for stripping organic material.
  12. Douglas Monte A. (Coppell TX), Selective etch method.
  13. Bartelink Dirk J. (Los Altos Hills CA), Strain relief flip-chip integrated circuit assembly with test fixturing.
  14. Kaeriyama Toshiyuki (Plano TX), Support posts for micro-mechanical devices.
  15. Kaeriyama Toshiyuki (Plano TX), Support posts for micro-mechanical devices.

이 특허를 인용한 특허 (24)

  1. Yeh Edward, Alternative plasma chemistry for enhanced photoresist removal.
  2. Leon Vincent G. ; Honda Kenji ; Rothgery Eugene F., Cleaning composition and method for removing residues.
  3. Shields Jeffrey A. ; Ko King Wai Kelwin ; Mercado Leobardo, Efficient in-situ resist strip process for heavy polymer metal etch.
  4. Kaichiu Wong ; Gregory M. McMahon, High vapor plasma strip methods and devices to enhance the reduction of organic residues over metal surfaces.
  5. Choi, Samuel S.; Li, Wai-kin, Lateral-dimension-reducing metallic hard mask etch.
  6. Gaynor, Justin F., Method and system for avoiding plasma etch damage.
  7. Mark Haley ; Delbert Parks ; Judy Galloway, Method for cleaning integrated circuit bonding pads.
  8. Cox, Gerald M.; Donoghue, John Kevin; Van Baekel, Kristel; Lee, Chan-Yun, Method for etching sidewall polymer and other residues from the surface of semiconductor devices.
  9. Tamaoka Eiji,JPX ; Aoi Nobuo,JPX ; Ueda Tetsuya,JPX, Method for fabricating semiconductor device.
  10. Shen, Yun-Hung, Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching.
  11. Tsai,Ming Huan; Chiang,Ru Chian; Tao,Hun Jan, Method for forming novel BARC open for precision critical dimension control.
  12. Liou, Shu-Hong H., Method for in-situ removal of photoresist and sidewall polymer.
  13. Christian Jehoul BE; Kristel Van Baekel BE; Werner Boullart BE; Herbert Struyf BE; Serge Vanhaelemeersch BE, Method for stripping ion implanted photoresist layer.
  14. Cho, Sung-Dong, Method of ashing semiconductor device having metal interconnection.
  15. Osamu Sugihara JP, Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board.
  16. Sugihara, Osamu, Method of manufacturing a contract element and a multi-layered wiring substrate, and wafer batch contact board.
  17. Cho, Jun Hee; Kim, Il Wook; Lee, Seok Kiu; Ahn, Tae Hang; Park, Sung Eon, Method of manufacturing semiconductor device.
  18. Berry, Ivan; Rounds, Stuart; Hallock, John; Owens, Michael; Dahimene, Mahmoud, Method of photoresist ash residue removal.
  19. Severac Didier,FRX ; Derie Michel,FRX, Method of removing polymeric material on a silicon water.
  20. Huang, Chuan-Chieh; Chang, Feng-Yueh; Lin, Chi-Lien, Method to improve via or contact hole profile using an in-situ polymer deposition and strip procedure.
  21. Mohammad R. Rakhshandehroo ; Mark S. Chang ; Angela T. Hui, Plasma treatment for polymer removal after via etch.
  22. Lebowitz Joseph ; Faulk Laura E., Residue removal by CO2 water rinse in conjunction with post metal etch plasma strip.
  23. Ueno, Kazuyoshi, Semiconductor device with improved stress migration resistance and manufacturing process therefor.
  24. Buchanan, Daryl; Tariq, Faisal; Mei, Hai; Tison, Stuart, System and method for producing and delivering vapor.
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