초록 ▼

An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower spee

An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower speed grade in the event that the integrated circuit fails the specifications of a targeted speed grade.

대표청구항 ▼

[ What is claimed is:] [1.] A memory device, comprising:memory control logic;a memory array having a plurality of memory cells for storing data, wherein the memory array produces a logic signal representing the stored data when addressed by the memory control logic;a delay element receiving the logi

[ What is claimed is:] [1.] A memory device, comprising:memory control logic;a memory array having a plurality of memory cells for storing data, wherein the memory array produces a logic signal representing the stored data when addressed by the memory control logic;a delay element receiving the logic signal from the output of the memory array and providing a delayed logic signal; anda multiplexer to selectively provide the logic signal and the delayed logic signal to an output interface as a function of a delay control.