초록 ▼

A microprocessor configured to detect a memory operation having a predefined data address is provided. The predefined data address indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, a second memory operation having the predefined data address indicates

A microprocessor configured to detect a memory operation having a predefined data address is provided. The predefined data address indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, a second memory operation having the predefined data address indicates that instructions subsequent to the second memory operation belong to the original instruction set. The memory operations effectively provide a boundary between the instructions from dissimilar instruction sets. Instructions are routed to an execution unit configured to execute the instruction set indicated by the most recently detected memory operation having the predefined address. Each instruction sequence within the program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. The program may be executed more quickly than an equivalent program coded entirely in either instruction set. In one embodiment, the microprocessor executes the x86 instruction set and the ADSP 2171 instruction set.

대표청구항 ▼

[ What is claimed is:] [1.] A microprocessor comprising:an instruction cache configured to store a plurality of instructions including a first plurality of instructions belonging to a first instruction set and a second plurality of instructions belonging to a second instruction set;an instruction de

[ What is claimed is:] [1.] A microprocessor comprising:an instruction cache configured to store a plurality of instructions including a first plurality of instructions belonging to a first instruction set and a second plurality of instructions belonging to a second instruction set;an instruction decode unit coupled to said instruction cache and configured to receive said plurality of instructions from said instruction cache, wherein said instruction decode unit is configured to decode said plurality of instructions; anda first register for storing a predefined data address, wherein said predefined data address is defined to indicate that a corresponding memory operation forms a boundary between said first plurality of instructions and said second plurality of instructions; anda load/store unit coupled to said instruction decode unit, wherein said load/store unit is configured to receive memory operations included within said plurality of instruction from said instruction decode unit, said load/store unit having an address generator configured to generate a data address for a memory operation, said load/store unit Also having an address detection circuit coupled to said address generator and configured to compare said predefined data address in said first register to said data address generated by said data address generator in order to detect said boundary, said load/store unit further having a second register configured to store an indication of which instruction set is being dispatched by said instruction decode unit, said load/store unit being configured to convey a first indication of said first instruction set to said instruction decode unit if said boundary is not detected and to convey a second indication to said instruction decode unit if said boundary is detected, and wherein said instruction decode unit is configured to decode instruction from said first instruction set upon receiving said first indication and to decode instructions from said second instruction set upon receiving said second indication.