$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Compiling system and method for reconfigurable computing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/18
  • G06F-019/00
출원번호 US-0827619 (1997-04-09)
발명자 / 주소
  • Greenbaum Jack E.
  • Baxter Michael A.
출원인 / 주소
  • Ricoh Company Ltd., JPX
대리인 / 주소
    Fenwick & West LLP
인용정보 피인용 횟수 : 162  인용 특허 : 4

초록 ▼

A compiling system and method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable among a plurality of hardware architectures, each hardware architecture executing instructio

대표청구항 ▼

[ What is claimed is:] [21.] A method of reconfiguring a dynamically reconfigurable processing unit during execution of a program comprising a sequence of program instructions, the method comprising:a) identifying a reconfiguration directive from the source code, the reconfiguration directive specif

이 특허에 인용된 특허 (4)

  1. Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
    상세보기
  2. Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
    상세보기
  3. Fontana James Albert ; Govindarajan Srinivasan, Method for generating OLE automation and IDL interfaces from metadata information.
    상세보기
  4. Boldo Irit (Neve Sheanan ILX) Shani Uri (Givat Adi ILX) Gold Israel (Haifa ILX), Programming system for generating client and server programs from an undistributed application program.
    상세보기

이 특허를 인용한 특허 (162)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
    상세보기
  10. Burger, Douglas C.; Smith, Aaron; Gray, Jan, Age-based management of instruction blocks in a processor instruction window.
    상세보기
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
    상세보기
  12. Hussain,Riaz Yousuf; John, Jr.,Chester Charles; Levine,Frank Eliot; Richardson,Christopher Michael, Apparatus and method for cataloging symbolic data for use in performance analysis of computer programs.
    상세보기
  13. Berry, Robert Francis; John, Jr., Chester Charles; Levine, Frank Eliot; Richardson, Christopher Michael; Urquhart, Robert J., Apparatus and method for generating a merged symbol file for verifying symbolic data.
    상세보기
  14. Tillmann, Axel; Novikov, Vladimir, Apparatus for encoding and decoding data according to a protocol specification.
    상세보기
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  19. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  20. Nathan, Adam D.; Montgomery, John I., Application retargeting.
    상세보기
  21. Goodwin, David William; Maydan, Dror; Chen, Ding-Kai; Petkov, Darin Stamenov; Tjiang, Steven Weng-Kiang; Tu, Peng; Rowen, Christopher, Automatic instruction set architecture generation.
    상세보기
  22. Goodwin, David William; Maydan, Dror; Chen, Ding-Kai; Petkov, Darin Stamenov; Tjiang, Steven Weng-Kiang; Tu, Peng; Rowen, Christopher, Automatic instruction set architecture generation.
    상세보기
  23. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
    상세보기
  24. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.
    상세보기
  25. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
    상세보기
  26. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
    상세보기
  27. Roberts James S., Compressing variable-length instruction prefix bytes.
    상세보기
  28. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
    상세보기
  29. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  30. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
    상세보기
  31. Crabill, Eric J., Configurable processor system.
    상세보기
  32. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
    상세보기
  33. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  34. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  35. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
    상세보기
  36. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  37. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
    상세보기
  38. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.
    상세보기
  39. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Data processor chip with flexible bus system.
    상세보기
  40. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
    상세보기
  41. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
    상세보기
  42. Baxter, Michael A., Documentation generation from a computer readable symbolic representation.
    상세보기
  43. Crosland,Andrew; May,Roger; Flaherty,Edward; Draper,Andrew, Embedded processor with watchdog timer for programmable logic.
    상세보기
  44. Rawsthorne,Alasdair; Sandham,John H.; Souloglou,Jason, Exception handling method and apparatus for use in program code conversion.
    상세보기
  45. Miller Paul K., Expanding instructions with variable-length operands to a fixed length.
    상세보기
  46. Gray, Jan; Burger, Doug; Smith, Aaron, Explicit instruction scheduler state information for a processor.
    상세보기
  47. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
    상세보기
  48. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
    상세보기
  49. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  50. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  51. Mahalingaiah Rupaka, Forcing regularity into a CISC instruction set by padding instructions.
    상세보기
  52. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
    상세보기
  53. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
    상세보기
  54. Lay, Ralf; Noffz, Klaus-Henning, Hardware programming and layout design.
    상세보기
  55. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  56. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  57. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  58. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  59. Shenderovich Georgiy,ILX, Hybrid computer programming environment.
    상세보기
  60. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  61. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
    상세보기
  62. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
    상세보기
  63. Burger, Doug, Locking operand values for groups of instructions executed atomically.
    상세보기
  64. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  65. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  66. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
    상세보기
  67. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
    상세보기
  68. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  69. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  70. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
    상세보기
  71. Burger, Douglas C.; Smith, Aaron; Gray, Jan, Mapping instruction blocks based on block size.
    상세보기
  72. Snider,Gregory S., Method and apparatus for compiling source code to configure hardware.
    상세보기
  73. Prinzing, Timothy N., Method and apparatus for using object files to provide reliable program operation.
    상세보기
  74. Garey, Kenneth E., Method and apparatus of selecting one of a plurality of predetermined configurations using only necessary bus widths based on power consumption analysis for programmable logic device.
    상세보기
  75. He, Haijian; Wu, Xiaohui; Fan, Wei, Method and device for dynamically loading relocatable file.
    상세보기
  76. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  77. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
    상세보기
  78. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
    상세보기
  79. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
    상세보기
  80. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  81. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  82. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  83. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
    상세보기
  84. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  85. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  86. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  87. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  88. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  89. Vorbach, Martin, Method for debugging reconfigurable architectures.
    상세보기
  90. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
    상세보기
  91. Vorbach,Martin, Method for debugging reconfigurable architectures.
    상세보기
  92. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
    상세보기
  93. Joly Christian ; Dolan Simon, Method for designing application specific integrated circuits.
    상세보기
  94. Axel Tillmann ; Vladimir Novikov, Method for encoding and decoding data according to a protocol specification.
    상세보기
  95. Shimura, Hiroshi, Method for forming a parallel processing system.
    상세보기
  96. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
    상세보기
  97. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  98. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
    상세보기
  99. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
    상세보기
  100. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
    상세보기
  101. Takahiro Moroda JP, Method of making link directive file and tool for making link directive file.
    상세보기
  102. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
    상세보기
  103. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  104. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  105. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  106. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  107. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
    상세보기
  108. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
    상세보기
  109. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
    상세보기
  110. Ebeling, W. H. Carl; Hogenauer, Eugene B., Method, system and software for programming reconfigurable hardware.
    상세보기
  111. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  112. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  113. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  114. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
    상세보기
  115. Vorbach, Martin, Methods and devices for treating and/or processing data.
    상세보기
  116. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Methods and systems for transferring data between a processing device and external devices.
    상세보기
  117. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
    상세보기
  118. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
    상세보기
  119. de Icaza, Miguel; Kumpera, Rodrigo; Pouliot, Sebastien; Kvinge, Rolf Bjarne; Bockover, Aaron Dean; Varga, Zoltan, Multi-sized data types for managed code.
    상세보기
  120. de Icaza, Miguel; Kumpera, Rodrigo; Pouliot, Sebastien; Kvinge, Rolf Bjarne; Bockover, Aaron Dean; Varga, Zoltan, Multi-sized data types for managed code.
    상세보기
  121. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
    상세보기
  122. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
    상세보기
  123. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  124. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
    상세보기
  125. Vorbach,Martin; M체nch,Robert, Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like).
    상세보기
  126. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
    상세보기
  127. Poznanovic, Daniel; Hammes, Jeffrey; Krause, Lisa; Steidel, Jon; Barker, David; Brooks, Jeffrey Paul, Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms.
    상세보기
  128. Burger, Doug; Smith, Aaron, Processing an encoding format field to interpret header information regarding a group of instructions.
    상세보기
  129. Snider,Gregory S., Processor and programmable logic computing arrangement.
    상세보기
  130. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
    상세보기
  131. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
    상세보기
  132. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
    상세보기
  133. Johnson,Luther A., Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compa.
    상세보기
  134. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
    상세보기
  135. Vorbach, Martin, Reconfigurable elements.
    상세보기
  136. Vorbach, Martin, Reconfigurable elements.
    상세보기
  137. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
    상세보기
  138. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
    상세보기
  139. Nickolls, John R.; Johnson, Scott D.; Williams, Mark; Mirsky, Ethan; Kirthiranjan, Kambdur; Pant, Amrit Raj; Madar, III, Lawrence J., Reconfigurable processing system and method.
    상세보기
  140. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  141. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  142. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  143. Vorbach, Martin, Reconfigurable sequencer structure.
    상세보기
  144. Vorbach,Martin, Reconfigurable sequencer structure.
    상세보기
  145. Pandit, Rakesh, Recording application consumption details.
    상세보기
  146. Van Gageldonk, Johan Sebastiaan Henri; Bekooij, Marco Jan Gerrit; Bink, Adrianus Josephus; Hoogerbrugge, Jan; Leijten, Jeroen Anton Johan; Mesman, Bart, Retargetable compiling system and method.
    상세보기
  147. Vorbach, Martin; Bretz, Daniel, Router.
    상세보기
  148. Vorbach,Martin; Bretz,Daniel, Router.
    상세보기
  149. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.
    상세보기
  150. Asai, Nobuhiro; Bordawekar, Rajesh R.; Shah, Ravi; Uenohara, Hayato, Running native code across single or multi-core hybrid processor achitecture.
    상세보기
  151. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
    상세보기
  152. Nandakumaraiah, Chandan Bellur, Searching computer programs that use different semantics.
    상세보기
  153. Forin, Alessandro; Lynch, Nathaniel L.; Rashid, Richard F., Software support for dynamically extensible processors.
    상세보기
  154. Master,Paul L.; Watson,John, Storage and delivery of device features.
    상세보기
  155. Beckmann,Carl J., Symbolic assembly language.
    상세보기
  156. Baumgart, Leona Dryden; Ehrman, John Robert; Lee, Richard E.; Lee, Barbara Ann, System and method using extended relocation types and operations in relocating operations.
    상세보기
  157. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
    상세보기
  158. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
    상세보기
  159. Kumar, Chandan; Kumar, Sanjeev, Systems and methods for dynamic struct variable creation including inline declaration with dynamic keys.
    상세보기
  160. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
    상세보기
  161. Paul K. Miller, Using padded instructions in a block-oriented cache.
    상세보기
  162. Pandit, Rakesh, Version compatibility determination.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로