초록 ▼

A method for scheduling and transmitting data cells includes providing a plurality of scheduling lists associated with a plurality of priorities that include a plurality of fields therein, assigning a virtual circuits to the scheduling lists by placing identifiers in some of the fields, sequentially

A method for scheduling and transmitting data cells includes providing a plurality of scheduling lists associated with a plurality of priorities that include a plurality of fields therein, assigning a virtual circuits to the scheduling lists by placing identifiers in some of the fields, sequentially indexing through the lists/fields, and transmitting specific data cells depending upon which identifier is indexed first given the priority of the scheduling lists. The method can include scheduling a next transmission time for a virtual circuit by determining an ideal time based a data rate associated with the virtual circuit, and placing an identifier in a field corresponding to the ideal time or the next available field within the scheduling list that the virtual circuit is assigned to. A scheduler includes a processor, an interface module and a buffer. The processor is configured to generate scheduling lists, assign virtual circuits to the scheduling lists, and index through the fields within the scheduling lists. The interface module allows the scheduler to access an external memory for storing the scheduling lists generated by the processor. The buffer is configured to transmit a data cell that is associated with an indexed virtual circuit over the network.

대표청구항 ▼

[ What is claimed is:] [1.] A method for scheduling ATM cells for transmission over a network, comprising:(a) providing a high-priority scheduling list having a plurality of high-priority fields therein, and a low-priority scheduling list having a plurality of low-priority fields therein;(b) assigni

[ What is claimed is:] [1.] A method for scheduling ATM cells for transmission over a network, comprising:(a) providing a high-priority scheduling list having a plurality of high-priority fields therein, and a low-priority scheduling list having a plurality of low-priority fields therein;(b) assigning a first virtual circuit to said high-priority scheduling list by placing a first identifier in a first field selected from said plurality of high-priority fields, and a second virtual circuit to said low-priority scheduling list by placing a second identifier in a second field selected from said plurality of low-priority fields;(c) sequentially indexing through said plurality of high-priority and low-priority fields at the same time with an indexing mechanism; and(d) outputting;(i) a first data cell associated with said first virtual circuit if said indexing mechanism indexes to said first field before reaching said second field;(ii) said first data cell if said indexing mechanism indexes to said first and second fields at the same time;(iii) a second data cell associated with said second virtual circuit if said indexing mechanism indexes to said second field before reaching said first field;wherein only one cell is output at one time.