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Tunable threshold SOI device using back gate well 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/01
출원번호 US-0092973 (1998-06-08)
발명자 / 주소
  • Burr James B.
  • Houston Theodore W.
출원인 / 주소
  • Texas Instruments, Inc.
대리인 / 주소
    Jones Volentine, LLP
인용정보 피인용 횟수 : 50  인용 특허 : 6

초록 ▼

A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor substrate and extends across the conductive w

대표청구항 ▼

[ What is claimed is:] [1.] An SOI device comprising:a semiconductor substrate;a conductive well of a first conductivity type formed in a principal surface of said semiconductor substrate;an insulating layer formed along said principal surface of said semiconductor substrate and extending across sai

이 특허에 인용된 특허 (6)

  1. Lee Kwing F. (Red Bank NJ) Ourmazd Abbas (Colts Neck NJ) Yan Ran-Hong (Aberdeen NJ), Insulated gate field-effect transistor with pulse-shaped doping.
    상세보기
  2. Burr James B. ; Brassington Michael P., Low power, high performance junction transistor.
    상세보기
  3. Burghartz Joachim Norbert, MOS high frequency switch circuit using a variable well bias.
    상세보기
  4. Mandelman Jack A. (Stormville NY), Method of fabricating low leakage SOI integrated circuits.
    상세보기
  5. Bahraman Ali (Palos Verdes Estates CA), Radiation hardened CMOS on SOI or SOS devices.
    상세보기
  6. Voldman Steven H. (Burlington VT) Tong Minh H. (Essex VT) Nowak Edward J. (Essex Junction VT) Geissler Stephen F. (Underhill VT), Semiconductor diode with silicide films and trench isolation.
    상세보기

이 특허를 인용한 특허 (50)

  1. Horigan, John W.; Gilbride, Daniel F.; Nguyen, Don J., Auto-calibrating voltage regulator with dynamic set-point capability.
    상세보기
  2. Chang, Leland; Ji, Brian L.; Kumar, Arvind; Majumdar, Amlan; Saenger, Katherine; Shi, Leathen; Yau, Jeng-Bang, Back-gated fully depleted SOI transistor.
    상세보기
  3. Burr, James B., Device including a resistive path to introduce an equivalent RC circuit.
    상세보기
  4. Burr, James B., Device including a resistive path to introduce an equivalent RC circuit.
    상세보기
  5. Burr, James B., Device including a resistive path to introduce an equivalent RC circuit.
    상세보기
  6. Burr, James B., Device including a resistive path to introduce an equivalent RC circuit.
    상세보기
  7. Burr, James B., Device including a resistive path to introduce an equivalent RC circuit.
    상세보기
  8. Berinder Brar, Field effect transistor and method for making the same.
    상세보기
  9. Brar, Berinder, Field effect transistor and method for making the same.
    상세보기
  10. Anderson, Brent A.; Hook, Terence B.; Na, Myung-Hee; Nowak, Edward J., Field effect transistor having delay element with back gate.
    상세보기
  11. Mouli,Chandra V., FinFET device with reduced DIBL.
    상세보기
  12. Mouli,Chandra V., FinFET device with reduced DIBL.
    상세보기
  13. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
    상세보기
  14. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
    상세보기
  15. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
    상세보기
  16. Forbes,Leonard, Fully depleted silicon-on-insulator CMOS logic.
    상세보기
  17. Bryant,Andres; Clark, Jr.,William F.; Nowak,Edward J., Hybrid orientation field effect transistors (FETs).
    상세보기
  18. Adamic ; Jr. Fred W., Integrated circuit including inverted dielectric isolation.
    상세보기
  19. Doyle Brian S. ; Roberds Brian ; Rios Rafael, Integrated circuit with dynamic threshold voltage.
    상세보기
  20. Burr, James B., Low voltage latch.
    상세보기
  21. Burr, James B., Low voltage latch with uniform sizing.
    상세보기
  22. James B. Burr, Low voltage latch with uniform stack height.
    상세보기
  23. Burr, James B., Method and structure for supply gated electronic components.
    상세보기
  24. James B. Burr, Method for coupling logic blocks using low threshold pass transistors.
    상세보기
  25. James B. Burr, Method for engineering the threshold voltage of a device using buried wells.
    상세보기
  26. Burr, James B., Method for introducing an equivalent RC circuit in a MOS device using resistive paths.
    상세보기
  27. Burr, James B., Method for supply gating low power electronic devices.
    상세보기
  28. Krishnan Srinath ; Buynoski Matthew S., Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer.
    상세보기
  29. Yamamoto,Naoki, Method of manufacturing a dual gate semiconductor device with a poly-metal electrode.
    상세보기
  30. Manning H. Montgomery, Methods of forming SOI insulator layers and methods of forming transistor devices.
    상세보기
  31. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  32. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  33. Manning H. Montgomery, Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies.
    상세보기
  34. Ning, Tak H.; Shahidi, Ghavam G.; Yau, Jeng-Bang, One time programmable read-only memory (ROM) in SOI CMOS.
    상세보기
  35. James B. Burr, Overdriven pass transistors.
    상세보기
  36. Hook, Terence B., Pseudo butted junction structure for back plane connection.
    상세보기
  37. Hook, Terence B., Pseudo butted junction structure for back plane connection.
    상세보기
  38. Mouli, Chandra V., SOI CMOS device with reduced DIBL.
    상세보기
  39. Mouli, Chandra V., SOI CMOS device with reduced DIBL.
    상세보기
  40. Mouli, Chandra V., SOI CMOS device with reduced DIBL.
    상세보기
  41. Mouli, Chandra V., SOI CMOS device with reduced DIBL.
    상세보기
  42. Mouli, Chandra V., SOI device with reduced drain induced barrier lowering.
    상세보기
  43. Mouli, Chandra V., SOI device with reduced drain induced barrier lowering.
    상세보기
  44. Mouli,Chandra V., SOI device with reduced drain induced barrier lowering.
    상세보기
  45. Srinath Krishnan ; Matthew Buynoski ; Witold Maszara, Selectively thin silicon film for creating fully and partially depleted SOI on same wafer.
    상세보기
  46. Manning H. Montgomery, Semiconductor devices and assemblies.
    상세보기
  47. Manning H. Montgomery, Semiconductor devices comprising semiconductive material substrates and insulator layers over the substrates.
    상세보기
  48. Zhu, Huilong; Liang, Qingqing; Luo, Zhijiong; Yin, Haizhou, Semiconductor structure and method for manufacturing the same.
    상세보기
  49. Vogelsang,Thomas, Standby current reduction over a process window with a trimmable well bias.
    상세보기
  50. Anderson, Brent A.; Nowak, Edward J., Structure and design structure having isolated back gates for fully depleted SOI devices.
    상세보기

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