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Methods apparatus and computer program products for accumulating logarithmic values 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/50
출원번호 US-0938410 (1997-09-26)
발명자 / 주소
  • Dent Paul Wilkinson
출원인 / 주소
  • Ericsson Inc.
대리인 / 주소
    Myers Bigel Sibley & Sajovec
인용정보 피인용 횟수 : 71  인용 특허 : 3

초록

The sum of a plurality of logarithmic numbers is determined by expressing the logarithmic numbers as one of a predetermined values. For example, the numbers may be analog values which may be sampled by an 8-bit AtoD converter to be expressed as one of a possible 256 values. The number of occurrences

대표청구항

[ That which is claimed is:] [1.] A method for summing a plurality of logarithmic numbers, the method comprising the steps of:expressing each of the plurality of logarithmic numbers as one of a predetermined number of values;accumulating a number of occurrences of each of the plurality of logarithmi

이 특허에 인용된 특허 (3)

  1. Williams Tim A. (Austin TX), Circuit for adding and/or subtracting numbers in logarithmic representation.
  2. Williams Tim A. (Austin TX), Logarithmic arithmetic logic unit.
  3. Williams Tim A. (Austin TX), Method and apparatus for minimizing a memory table for use with nonlinear monotonic arithmetic functions.

이 특허를 인용한 특허 (71)

  1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
  2. Langhammer, Martin, Angular range reduction in an integrated circuit device.
  3. Tiwari, Jeet Narayan; Gupta, Nitin, Asynchronous high-speed programmable divider.
  4. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  5. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  6. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  7. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  8. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
  9. Langhammer, Martin, Combined floating point adder and subtractor.
  10. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
  11. Dent, Paul Wilkinson, Complex logarithmic ALU.
  12. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
  13. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
  14. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
  15. Langhammer, Martin, Configuring floating point operations in a programmable device.
  16. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
  17. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
  18. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  19. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  20. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  21. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  22. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  23. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  24. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  25. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
  26. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
  27. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
  28. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
  29. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
  30. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
  31. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
  32. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  33. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  34. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  35. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  36. Ryan, Philip J., Linear-to-log converter for power estimation in a wireless data network receiver.
  37. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  38. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  39. Langhammer, Martin, Matrix operations in an integrated circuit device.
  40. Dent, Paul Wilkinson, Memory compression.
  41. Jennings, III, Earle Willis, Method and apparatus for narrow to very wide instruction generation for arithmetic circuitry.
  42. Romme, Jacobus Petrus Adrianus; Kajiwara, Keishi, Method and device for calculating average received power.
  43. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  44. Portell I De Mora, Jordi; Garcíaberro Montilla, Enrique; Luri Carrascoso, Xavier; González Villafranca, Alberto; Torra Roca, Jorge, Method for fully adaptive calibration of a prediction error coder.
  45. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  46. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  47. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  48. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  49. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  50. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  51. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  52. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  53. Dent, Paul Wilkinson, Pipelined real or complex ALU.
  54. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  55. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
  56. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  57. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
  58. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
  59. Langhammer, Martin, QR decomposition in an integrated circuit device.
  60. Mauer, Volker, QR decomposition in an integrated circuit device.
  61. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
  62. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
  63. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
  64. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  65. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
  66. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
  67. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
  68. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  69. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
  70. Dent, Paul W., Systems and methods for communicating spread spectrum signals using variable signal constellations.
  71. Paul W. Dent, Tailbiting decoder and method.
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