초록 ▼

A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. T

A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

대표청구항 ▼

[ We claim:] [1.] A static random access memory cell comprising:a voltage terminal;means for storing a binary value coupled to the voltage terminal comprising two cross-coupled inverters;a select gate having a first terminal coupled to the means for storing and a second terminal, wherein the select

[ We claim:] [1.] A static random access memory cell comprising:a voltage terminal;means for storing a binary value coupled to the voltage terminal comprising two cross-coupled inverters;a select gate having a first terminal coupled to the means for storing and a second terminal, wherein the select gate is further characterized as being a transmission gate which comprises at least one thin film transistor (TFT) overlying another transistor; anda conductor coupled to the second terminal of the select gate to bit line detection circuitry.