초록 ▼

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

대표청구항 ▼

[ What is claimed is:] [1.] A selective read capture latch for selectively interfacing a hierarchical bit line structure, said selective read capture latch comprising:at least first and second hierarchy inputs for receiving data from respective first and second hierarchy bit lines of the hierarchica

[ What is claimed is:] [1.] A selective read capture latch for selectively interfacing a hierarchical bit line structure, said selective read capture latch comprising:at least first and second hierarchy inputs for receiving data from respective first and second hierarchy bit lines of the hierarchical bit line structure;a memory unit having an input and output, said memory unit for retaining data per data received at its input, and providing output data at its output per data retained therein; andselective coupling means between said at least first and second hierarchy inputs and said input of said memory unit, for selectively coupling one of said first and second hierarchy inputs to said input of said memory unit for propagating data therebetween in accordance with an associated hierarchy read capture clock.