$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Dual substrate package assembly coupled to a conducting member 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/14
  • H01R-023/68
출원번호 US-0999841 (1996-05-24)
발명자 / 주소
  • Dranchak David William
  • Kelleher Robert Joseph
  • Pagnani David Peter
  • Zippetelli Patrick Robert
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ratner & PrestiaFraley
인용정보 피인용 횟수 : 78  인용 특허 : 22

초록

An electronic package assembly for being electrically connected to a conducting member (e.g., a printed circuit board) wherein the assembly includes a pair of substrates. The first substrate includes opposing circuit patterns, those on one surface being of higher density and thus adapted for having

대표청구항

[ What is claimed is:] [1.] An electronic package assembly for being electrically coupled to a conducting member having a plurality of first receiving conductors, said package assembly comprising:a first substrate including a first surface having an electrical pattern thereon of a first density, a s

이 특허에 인용된 특허 (22)

  1. White Robert C. (Cliffside Park NJ), Area and edge array electrical connectors.
  2. Ahmad Umar M. U. (Hopewell Junction NY) Bross Arthur (Poughkeepsie NY) Czornyj George (Poughkeepsie NY) Harrison Harry K. (Poughkeepsie NY) Jones Richard R. (Kerhonkson NY), Array of pinless connectors and a carrier therefor.
  3. Weinold Christoffer S. (1307 Ridge Rd. Vista CA 92083), DIP switch with built-in active interfacing circuitry.
  4. Yamazaki Kouichi (Nagano JPX) ..AP: Shin-Etsu Polymer Co. ; Ltd. (Tokyo JPX 03), Elastic interconnector.
  5. Gilissen Hermanus Petrus Johannes (Esch NL) VAN Dijk Petrus Richardus Martinus (\S-Hertogenbosch NL), Elastomeric connector and its method of manufacture.
  6. Zifcak Mark S. (Putnam CT) Kosa Bruce G. (Woodstock CT), Electrical circuit board interconnect.
  7. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  8. Busacco Raymond A. (Lake Ariel PA) Chang Chi S. (Endicott NY) Chapin Fletcher W. (Vestal NY) Dranchak David W. (Endwell NY) Macek Thomas G. (Endicott NY) Petrozello James R. (Endicott NY) Saxenmeyer , High density connector.
  9. Chapin Fletcher W. (Vestal NY) Dranchak David W. (Endwell NY) Engle David E. (Vestal NY) Hall Richard R. (Endwell NY) Macek Thomas G. (Endicott NY), High density connector.
  10. Gow ; 3rd John (Milton VT) Noth Richard W. (Fairfax VT), High performance versatile thermally enhanced IC chip mounting.
  11. Miller ; Jr. Grady A. (Grand Prairie TX), Method and apparatus for attaching a circuit component to a printed circuit board.
  12. Busacco Raymond A. (Lake Ariel PA) Chapin Fletcher W. (Vestal NY) Dranchak David W. (Endwell NY) Molla Jaynal A. (Endicott NY) Saxenmeyer ; Jr. George J. (Apalachin NY) Topa Robert D. (Binghamton NY), Method of forming a conductive end portion on a flexible circuit member.
  13. Werther William E. (Wood Ranch CA), Multi-level assemblies for interconnecting integrated circuits.
  14. Adachi, Kazumasa; Takahashi, Shinji; Hirabayashi, Kimitaka, Package for surface mounted components.
  15. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Packaged semiconductor device having a low cost ceramic PGA package.
  16. Chiang Jung-Shan (Taipei TWX), Pin grid array adaptor mounting hardware.
  17. Braun Randall E. (Santa Cruz CA), Pin grid array assembly.
  18. Haville George D. (Santa Barbara CA), Positional encoders with plug-together modules.
  19. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  20. Ganthier James J. (Spring TX), Space-saving mounting interconnection between electrical components and a printed circuit board.
  21. Menzies ; Jr. L. William (938 Pleasant Hill Rd. Redwood City CA 94061) Menzies Stephen W. (4906 Colusa St. Union City CA 94587), Surface mounted decoupling capacitor.
  22. Golubic Theodore R. (Phoenix AZ), Three dimensional interconnected integrated circuit.

이 특허를 인용한 특허 (78)

  1. Goodwin,Paul; Wehrly, Jr.,James Douglas, Active cooling methods and apparatus for modules.
  2. Johnson, Kenneth William, Back side probing method and assembly.
  3. Goodwin,Paul, Buffered thin module system and method.
  4. Hirakawa, Tetsuo, Ceramic circuit board.
  5. Frutschy, Kristopher; Stewart, Glenn E.; Yahyaei-Moayyed, Farzaneh; Reid, Geoffery L., Circuit housing clamp and method of manufacture therefor.
  6. Szewerenko, Leland; Partridge, Julian; Lieberman, Wayne; Goodwin, Paul, Circuit module turbulence enhancement systems and methods.
  7. Wehrly, Jr.,James Douglas; Wilder,James; Wolfe,Mark; Goodwin,Paul, Circuit module with thermal casing systems.
  8. Cady, James W.; Wehrly, Jr., James Douglas; Goodwin, Paul, Compact module system and method.
  9. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  10. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  11. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  12. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
  13. Cady, James W.; Goodwin, Paul, Die module system.
  14. Cady,James W.; Goodwin,Paul, Die module system.
  15. Stoermer, Peter, Electrical connection arrangement.
  16. Eldridge, Benjamin N.; Wenzel, Stuart W., Electronic components with plurality of contoured microelectronic spring contacts.
  17. Christo, Michael A.; Maldonado, Julio A.; Weekly, Roger D.; Zhou, Tingdong, Electronic module power supply.
  18. Christo, Michael A.; Maldonado, Julio A.; Weekly, Roger D.; Zhou, Tingdong, Electronic module power supply.
  19. Tamura Koetsu,JPX, Electronic-circuit assembly.
  20. Patel, Chirag S., Fabrication of semiconductor dies with micro-pins and structures produced therewith.
  21. Thomas, John; Rapport, Russell; Washburn, Robert, Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area.
  22. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
  23. Cady, James W.; Wilder, James; Roper, David L.; Wehrly, Jr., James Douglas, Flex-based circuit module.
  24. Matsuo, Tsutomu, Flexible circuit board connecting device.
  25. Pierson, Mark Vincent; Sweterlitsch, Jennifer Rebecca; Woychik, Charles Gerard; Youngs, Jr., Thurston Bryce, Floating interposer.
  26. Wehrly, Jr., James Douglas; Wilder, James; Goodwin, Paul; Wolfe, Mark, Heat sink for a high capacity thin module system.
  27. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  28. Wehrly, Jr.,James Douglas; Wilder,James; Goodwin,Paul; Wolfe,Mark, High capacity thin module system.
  29. Goodwin, Paul, High capacity thin module system and method.
  30. Goodwin, Paul, High capacity thin module system and method.
  31. Goodwin,Paul, High capacity thin module system and method.
  32. Conn, Robert O., Integral metal structure with conductive post portions.
  33. Bernstein, Gary H.; Fay, Patrick; Porod, Wolfgang; Liu, Qing, Inter-chip communication.
  34. Bernstein, Gary H.; Fay, Patrick; Porod, Wolfgang; Liu, Qing, Inter-chip communication.
  35. Bernstein, Gary H.; Fay, Patrick; Porod, Wolfgang; Lui, Qing, Inter-chip communication.
  36. Koide, Masateru, Interconnect board, printed circuit board unit, and method.
  37. Bernstein, Gary H.; Fay, Patrick; Porod, Wolfgang; Liu, Qing, Interconnect packaging systems.
  38. Taylor, Paul R., Interposer assembly and method.
  39. Hamasaki, Hiroshi; Furuyama, Hideto, LSI package with interface module and interface module.
  40. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  41. Wehrly, Jr.,James Douglas; Orris,Ron; Szewerenko,Leland; Roy,Tim; Partridge,Julian; Roper,David L., Managed memory component.
  42. Wehrly, Jr., James Douglas, Memory card and method for devising.
  43. Wehrly, Jr., James Douglas, Memory card and method for devising.
  44. Goodwin, Paul, Memory module system and method.
  45. Heston, Matthew L.; Theodoras, II, James T., Method and apparatus for coupling circuit boards.
  46. Frederic M. Kozak ; Real Gislain Pomerleau, Method and apparatus for decoupling ball grid array devices.
  47. Ohtaki, Mikio, Method for manufacturing and batch testing semiconductor devices.
  48. Ohtaki,Mikio, Method for manufacturing and testing semiconductor devices on a resin-coated wafer.
  49. Ohtaki, Mikio, Method of testing circuit elements on a semiconductor wafer.
  50. Partridge, Julian; Roper, David; Goodwin, Paul, Modified core for circuit module system and method.
  51. Goodwin, Paul; Cady, James W., Module thermal management system and method.
  52. Dalal, Hormazdyar M.; Gaudenzi, Gene Joseph, Multi-level electronic package and method for making same.
  53. Wehrly, Jr., James Douglas; Wolfe, Mark; Goodwin, Paul, Optimized mounting area circuit module system and method.
  54. Roper,David L.; Cady,James W.; Wilder,James; Wehrly, Jr.,James Douglas; Buchle,Jeff; Dowden,Julian, Pitch change and chip scale stacking system and method.
  55. Shiffer,Stephen R., Plastic leadframe and compliant fastener.
  56. Frutschy, Kristopher; Stewart, Glenn E.; Yahyaei-Moayyed, Farzaneh; Reid, Geoffrey L., Printed circuit board housing clamp.
  57. Tohru Ohtaki JP; Tohru Ohsaka JP, Printed wiring board unit for use with electronic apparatus.
  58. Hall, Douglas C.; Howard, Scott; Hoffman, Anthony; Bernstein, Gary H.; Kulick, Jason M., Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment.
  59. Mikio Ohtaki JP, Semiconductor device test apparatus.
  60. Kato, Yousif; Vesey, Jeff, Small pitch ball grid array of a package assembly for use with conventional burn-in sockets.
  61. Sathe, Ajit V.; Wermer, Paul H., Solderless electronics packaging.
  62. Sathe,Ajit V.; Wermer,Paul H., Solderless electronics packaging and methods of manufacture.
  63. Roper, David L.; Wehrly, Jr., Douglas; Wolfe, Mark, Split core circuit module.
  64. Szewerenko,Leland; Goodwin,Paul; Wehrly, Jr.,James Douglas, Stackable micropackages and stacked modules.
  65. Wehrly, Jr.,James Douglas, Stacked integrated circuit module.
  66. Partridge, Julian; Wehrly, Jr., James Douglas; Roper, David L.; Villani, Joseph, Stacked module systems.
  67. Partridge,Julian; Wehrly, Jr.,James Douglas; Roper,David, Stacked module systems and method.
  68. Roeters,Glen E; Ross,Andrew C, Stacking system and method.
  69. Bily Wang TW, Surface mount package for long lead devices.
  70. Pai, Deepak K., System and method of using a compliant lead interposer.
  71. Liao, Peter; Takacs, Zsolt G., Termination board for mounting on circuit board.
  72. Ortman, Stephen Bernard; Amor, Amador Miguel; Dinh, Lam Tung, Test adapter for configuring the electrical communication between a unit under test and an electronic test station and associated separator plate.
  73. Eldridge,Benjamin N.; Wenzel,Stuart W., Test head assembly having paired contact structures.
  74. Goodwin, Paul; Cady, James W.; Wehrly, Douglas, Thin module system and method.
  75. Goodwin,Paul, Thin module system and method.
  76. Goodwin,Paul, Thin module system and method.
  77. Heenan, Bryan Timothy, Vertical cache configuration.
  78. Momokawa, Yuki, Wiring board, and electronic device with an electronic part mounted on a wiring board, as well as method of mounting an electronic part on a wiring board.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로