초록 ▼

A memory management system for a fault tolerant computer system. The memory management system includes a first recording mechanism which can be activated to record memory update events; a second recording mechanism which records at least a limited number of memory update events; a fault input for a

A memory management system for a fault tolerant computer system. The memory management system includes a first recording mechanism which can be activated to record memory update events; a second recording mechanism which records at least a limited number of memory update events; a fault input for a fault signal to activate the first recording mechanism in the event of a fault event; and a memory reintegration mechanism to reintegrate at least parts of memory identified in the first and second recording mechanisms. Preferably, the recording of memory updates (writes) is not based on recording each address accessed, but rather on memory segments (pages) updated (written to). Further, a fault tolerant computer system includes a plurality of synchronous processing sets, each having a processor with internal memory and operating in lockstep, and an out of sync detector for detecting an out-of-sync-event and for generating an out-of-sync signal.

대표청구항 ▼

[ What I claim is:] [10.] A fault tolerant computer system comprising a plurality of synchronous processing sets, each comprising a processor and internal memory and operating in lockstep, and an out-of-sync detector for detecting an out-of-sync event and for generating an out-of-sync signal, wherei

[ What I claim is:] [10.] A fault tolerant computer system comprising a plurality of synchronous processing sets, each comprising a processor and internal memory and operating in lockstep, and an out-of-sync detector for detecting an out-of-sync event and for generating an out-of-sync signal, wherein each processing set also comprises:a first recording mechanism which can be activated to record memory write events;a fault input for receiving said out-of-sync signal to activate said first recording mechanism in the event of said out-of-sync event;a second recording mechanism having a capacity to record at least a limited number of memory write events, and to maintain a record of recent memory update events up to a number sufficient to cover the time to activate said first recording mechanism following said out-of-sync event, said second recording mechanism comprises a first-in-first-out buffer, an output of said first-in-first-out buffer is connected to said first recording mechanism, and a further said first-in-first-out buffer stores up to a predetermined number of update addresses, an address decoder is connected to said output of said first-in-first out buffer to generate a page signal representative of a memory update address output from said first-in-first-out buffer and said address decoder is responsive to said out-of-sync signal to pass said page signal to said first recording mechanism; anda memory reintegration mechanism to reintegrate in an out-of-sync processing set at least parts of memory identified in said first and second recording mechanisms.