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Trench/hole fill processes for semiconductor fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/441
출원번호 US-0689535 (1996-08-09)
발명자 / 주소
  • Elliott Richard L.
  • Givens John H.
  • Hudson Guy F.
출원인 / 주소
  • MICRON Technology, Inc.
대리인 / 주소
    Workman, Nydegger & Seeley
인용정보 피인용 횟수 : 45  인용 특허 : 15

초록

A contact space filled with conductive material having good step coverage is disclosed. The contact space is formed in a dielectric layer with an upper surface. The contact space has sidewalls comprised of the dielectric layer and a bottom comprised of an underlying layer. The contact space is fille

대표청구항

[ What is claimed and desired to be secured by United States Letters Patent is:] [1.] A method of forming a contact structure comprising:forming, through a dielectric layer having a top surface, a contact space to be filled, said contact space having sidewalls and a bottom, said contact space exposi

이 특허에 인용된 특허 (15)

  1. Hamajima Kaneo (Toyota JPX) Tanaka Atsuo (Toyota JPX) Dohnomoto Tadashi (Toyota JPX) Fuwa Yoshio (Toyota JPX) Michioka Hirohumi (Toyota JPX), Aluminum alloy composite material with intermetallic compound finely dispersed in matrix among reinforcing elements.
  2. Ward Michael G. (1 Haven Ct. ; #S-3B Nyack NY 10960), Filling of vias and contacts employing an aluminum-germanium alloy.
  3. Eizenberg Moshe (Kiryat-Ata NJ ILX) Murarka Shyam P. (New Providence NJ), Forming low-resistance contact to silicon.
  4. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  5. Yu Chang (Boise ID), Method for improving step coverage of a metallization layer on an integrated circuit by use of molybdenum as an anti-ref.
  6. Lee Pei-Ing P. (32 Stirrup Cir. Williston VT 05495) Licata Thomas J. (161 Austin Dr. #1 Burlington VT 05401) McDevitt Thomas L. (R.R. #2 ; Box 3230 Underhill VT 05489) Parries Paul C. (32 Tanglewood , Method of depositing conductors in high aspect ratio apertures using a collimator.
  7. Howard James K. (Fishkill NY) Rosenberg William D. (Wappingers Falls NY) White James F. (Newburgh NY), Method of fabricating improved Schottky barrier contacts.
  8. Fujii Hiroyuki (Hyogo JPX) Harada Shigeru (Hyogo JPX), Method of manufacturing semiconductor device having multilayer interconnection structure.
  9. Sun Shi-Chung (Taipei TWX) Chiu Hien-Tien (Taipei TWX) Tsai Ming-Hsing (Chiayi TWX), Process for fabricating tantalum nitride diffusion barrier for copper matallization.
  10. Hu Yongjun (Boise ID), Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium.
  11. Yamada Yoshiaki (Tokyo JPX) Ito Nobukazu (Tokyo JPX) Miyakawa Kuniko (Tokyo JPX) Yamanaka Michiko (Tokyo JPX), Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring.
  12. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  13. Murakami Masanori (Goldens Bridge NY) Price William H. (E. Rockaway NY), Thermally stable ohmic contact for gallium-arsenide.
  14. Yokoyama Natsuki (Mitaka JPX) Homma Yoshio (Tokyo JPX) Hinode Kenji (Hachioji JPX) Mukai Kiichiro (Hachioji JPX), Titanium nitride film in contact hole with large aspect ratio.
  15. Xu Zheng (Foster City CA) Chen Fusen (Cupertino CA), Ultrasonic wave assisted contact hole filling.

이 특허를 인용한 특허 (45)

  1. Kadosh Daniel ; Gardner Mark I., Asymmetrical IGFET devices with spacers formed by HDP techniques.
  2. Fleming, Robert; Graydon, Bhret; Vasquez, Daniel; Wu, Junjun; Razavi, Farhad, Circuit elements comprising ferroic materials.
  3. Kosowsky, Lex; Graydon, Bhret; Fleming, Robert, Components having voltage switchable dielectric materials.
  4. Kosowsky, Lex, Current-carrying structures fabricated using voltage switchable dielectric materials.
  5. Kosowsky, Lex; Fleming, Robert, Device applications for voltage switchable dielectric material having high aspect ratio particles.
  6. Kosowsky, Lex; Fleming, Robert, Device applications for voltage switchable dielectric material having high aspect ratio particles.
  7. Chung-Shi Liu TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Effective diffusion barrier.
  8. Kosowsky, Lex; Fleming, Robert; Graydon, Bhret; Vasquez, Daniel, Electric discharge protection for surface mounted and embedded components.
  9. Kosowsky, Lex; Fleming, Robert, Electronic device for voltage switchable dielectric material having high aspect ratio particles.
  10. Kosowsky, Lex; Fleming, Robert; Graydon, Bhret; Vasquez, Daniel, Embedded protection against spurious electrical events.
  11. Kosowsky, Lex; Fleming, Robert, Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same.
  12. Kosowsky, Lex; Fleming, Robert, Formulations for voltage switchable dielectric materials having a stepped voltage response and methods for making the same.
  13. Kosowsky, Lex; Fleming, Robert; Shi, Ning, Geometric and electric field considerations for including transient protective material in substrate devices.
  14. Kosowsky, Lex; Fleming, Robert, Geometric configuration or alignment of protective material in a gap structure for electrical devices.
  15. Kosowsky, Lex, Light-emitting device using voltage switchable dielectric material.
  16. Kosowsky, Lex; Fleming, Robert, Light-emitting diode device for voltage switchable dielectric material having high aspect ratio particles.
  17. Rhodes,Howard E., Local multilayered metallization.
  18. Rhodes,Howard E., Local multilayered metallization.
  19. Kosowsky, Lex; Fleming, Robert, Method for electroplating a substrate.
  20. Hegde Rama I. ; Denning Dean J. ; Klein Jeffrey L. ; Tobin Philip J., Method for forming a conductive structure having a composite or amorphous barrier layer.
  21. Avanzino Steven C. ; Sahota Kashmir S. ; Marxsen Gerd, Method for multiple phase polishing of a conductive layer in a semidonductor wafer.
  22. Huang Yimin,TWX ; Yew Tri-Rung,TWX, Method of forming bonding pad.
  23. Richard Philip Surprenant ; Edward Sumner Begle ; Nancy Wagner Hannon ; Mathias Pierre Jeanneret, Method of forming recessed thin film landing pad structure.
  24. Chan Lap ; Zheng Jia Zhen,SGX, Method of making a copper interconnect with top barrier layer.
  25. Chung-Shi Liu TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process.
  26. Kosowsky, Lex, Methods for fabricating current-carrying structures using voltage switchable dielectric materials.
  27. Kosowsky,Lex, Methods for fabricating current-carrying structures using voltage switchable dielectric materials.
  28. Rueger, Neal R.; Budge, William; Li, Weimin, Protection in integrated circuits.
  29. Rueger,Neal R.; Budge,William; Li,Weimin, Protection in integrated circuits.
  30. Berger, II, Robert E.; Kumar, Binod, Resistors formed of aluminum-titanium alloys.
  31. Huang, Hsin-Fu; Lin, Kun-Hsien; Hsu, Chi-Mao; Tsai, Min-Chuan; Lee, Tzung-Ying; Lin, Chin-Fu, Semiconductor device.
  32. Matsubara, Yoshihisa, Semiconductor device and manufacturing method of the same.
  33. Huang, Hsin-Fu; Lin, Kun-Hsien; Hsu, Chi-Mao; Tsai, Min-Chuan; Lee, Tzung-Ying; Lin, Chin-Fu, Semiconductor device and method of fabricating the same.
  34. Kosowsky, Lex, Semiconductor devices including voltage switchable materials for over-voltage protection.
  35. Kosowsky, Lex; Fleming, Robert; Graydon, Bhret, Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration.
  36. Fleming, Robert; Kosowsky, Lex; Shang, Shurui; Graydon, Bhret; Chen, Xiaofeng; Irvin, Glen, Substrates having voltage switchable dielectric materials.
  37. Kosowsky, Lex; Graydon, Bhret; Moustafaev, Djabbar; Shang, Shurui; Fleming, Robert, Substrates having voltage switchable dielectric materials.
  38. Shang, Shurui; Fleming, Robert, Substrates having voltage switchable dielectric materials.
  39. Kosowsky, Lex; Fleming, Robert, System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices.
  40. Lu, Jiong-Ping; Hong, Qi-Zhong; Chiu, Tz-Cheng; Jin, Changming; Permana, David; Tsui, Ting, System for improving thermal stability of copper damascene structure.
  41. Givens,John H., Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure.
  42. John H. Givens, Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure.
  43. Kosowsky, Lex; Fleming, Robert; Wu, Junjun; Saraf, Pragnya; Ranganathan, Thangamani, Voltage switchable dielectric material containing conductive core shelled particles.
  44. Kosowsky, Lex; Fleming, Robert; Wu, Junjun; Saraf, Pragnya; Ranganathan, Thangamani, Voltage switchable dielectric material containing conductor-on-conductor core shelled particles.
  45. Kosowsky, Lex; Fleming, Robert, Voltage switchable dielectric material having bonded particle constituents.
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