초록 ▼

A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit co

A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit. The pulse generator circuit is operative to receive a clock signal and generate a pulse in response to a first transition of the clock signal. The clocked comparator is coupled to the pulse generator circuit and operative to receive the pulse. The clocked comparator determines the state of the slew rate control signal by sampling for the pulse in response to a second transition of the clock signal.

대표청구항 ▼

[ What is claimed is:] [1.] A driver circuit having a controlled slew rate, comprising:a first circuit having an input coupled to receive a data signal and an output operative to output a drive signal in response to the data signal;a second circuit coupled in parallel with the first circuit and oper

[ What is claimed is:] [1.] A driver circuit having a controlled slew rate, comprising:a first circuit having an input coupled to receive a data signal and an output operative to output a drive signal in response to the data signal;a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; anda slew rate indicator circuit coupled to the second circuit, the slew rate indicator circuit determining the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, then the second circuit is enabled to affect the slew rate of the drive signal, wherein the slew rate indicator circuit comprises:a one-shot circuit operative to receive a clock signal, the one-shot circuit generating a pulse in response to a first transition of the clock signal; anda clocked comparator coupled to the one-shot circuit and operative to receive the pulse, the clocked comparator determining the state of the slew rate control signal by sampling for the presence of the pulse in response to a second transition of the clock signal.