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Method and apparatus for providing optimization parameters to a logic optimizer tool 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/60
출원번호 US-0752619 (1996-11-19)
발명자 / 주소
  • Cleereman Kevin C.
  • Merryman Kenneth E.
출원인 / 주소
  • Unisys Corporation
대리인 / 주소
    Johnson
인용정보 피인용 횟수 : 5  인용 특허 : 32

초록

A method and apparatus for providing optimization parameters to an EDA logic optimizing tool. The optimization parameters for selected circuit modules within a circuit design database may be stored such that a particular optimization parameter set can be uniquely identified by a search capability of

대표청구항

[ We claim:] [1.] A data processing system for optimizing a circuit design stored in a circuit design database, the circuit design database including a number of circuit modules wherein the optimization of selected ones of the number of circuit modules is selectively influenced by corresponding ones

이 특허에 인용된 특허 (32)

  1. Kawata Tetsuro (Kanagawa JPX), Apparatus for optimizing hierarchical circuit data base and method for the apparatus.
  2. Baisuck Allen (San Jose CA) Fairbank Richard L. (Schenectady NY) Gowen ; III Walter K. (Troy NY) Henriksen Jon R. (Latham NY) Hoover ; III William W. (Ballston Lake NY) Huckabay Judith A. (Union City, Architecture and method for data reduction in a system for analyzing geometric databases.
  3. Chao Chente (Irvine CA) Itkis Michail Y. (Redondo Beach CA), Automated circuit design method.
  4. Saucier Gabriele (Bresson FRX) Poirot Franck J. (Valbonne FRX), Automatic synthesis of integrated circuits employing controlled input dependency during a decomposition process.
  5. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Bitwise implementation mechanism for a circuit design synthesis procedure.
  6. Igarashi Shinichi (Tokyo JPX), CAD system for generating a schematic diagram of identifier sets connected by signal bundle names.
  7. Talbott Marvin T. (Plano TX) Hutchison Katherine K. (Dallas TX), Computer tool for system level design.
  8. Hooper Donald F. (Northboro MA), Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design.
  9. Kamijima Shinji (Tokyo JPX), Floor-planning apparatus for hierarchical design of LSI.
  10. Seyler Mark R. (Portland OR), Graph-based programming system and associated method.
  11. Modarres Hossein (Mountain View CA) Raam Susan (Fremont CA) Lai Jiun-Hao (Santa Clara CA), Hierarchical floorplanner.
  12. Mastellone Mitchel A. (New Brunswick NJ), Hierarchical net list derivation system.
  13. Do Cuong (San Jose CA) Wei Ruey-Sing (Fremont CA), Hierarchical ordering of logical elements in the canonical mapping of net lists.
  14. Rubin Steven M. (Portola Valley CA), Integrated electric design system with automatic constraint satisfaction.
  15. Talbott Marvin T. (Plano TX) Burks Henry L. (Dallas TX) Shaw Richard W. (Plano TX) Amundsen Michael (Dallas TX) Hutchison Katherine K. (Dallas TX) Strasburg Donald D. (Plano TX), Method and apparatus for aiding system design.
  16. Kionka Daniel P. (San Jose CA), Method and apparatus for optimizing computer file compilation.
  17. Carmean Douglas (Beaverton OR) Mundkur Yatin (Austin TX), Method and apparatus for optimizing electronic circuits.
  18. Sharma Balmukund K. (Santa Clara CA) Mahmood Mossaddeq (San Jose CA), Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication.
  19. Talbott Marvin T. (Plano TX) Burks Henry L. (Dallas TX) Shaw Richard W. (Plano TX) Strasburg Donald D. (Plano TX) Hutchison Katherine K. (Dallas TX), Method and apparatus for system design.
  20. Kim Michelle Y. (Scarsdale NY), Method and system for providing a non-rectangular floor plan.
  21. Matsunaga Yusuke (Yokohama JPX), Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing per.
  22. Morita Masato (Hadano JPX) Ikariya Yukio (Hadano JPX) Sakataya Yoshinori (Hadano JPX) Miyoshi Masayuki (Hadano JPX), Method for generating logic circuit data.
  23. Knapp Steven K. (Santa Clara CA) Seidel Jorge P. (San Jose CA) Kelem Steven H. (Los Altos Hills CA), Method for generating logic modules from a high level block diagram.
  24. Petrus Edwin S. (Santa Clara CA), Method for preparing and dynamically loading context files.
  25. Nishiyama Tamotsu (Hirakata JPX) Ikeda Kazushi (Tsu JPX) Matsunaga Tomoko (Kumamoto JPX), Method of and system for automatically generating network diagrams.
  26. Altheimer Michel (Antibes FRX) Gravoulet Valery F. (Valbonne FRX) Holt Paul M. (Antibes FRX) Riherd Frank T. (Nice FRX), Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler includi.
  27. Sturges Jay J. (Orangevale CA), Process oriented logic simulation having stability checking.
  28. Lee Kaiwin (Sunnyvale CA) Chung Lu (Sunnyvale CA) Lin Chin-Hsen (Milpitas CA) Liao Yuh-Zen (Saratoga CA) Wuu Stephen (Sunnyvale CA), Routing algorithm method for standard-cell and gate-array integrated circuit design.
  29. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Rule structure in a procedure for synthesis of logic circuits.
  30. Dangelo Carlos (Los Gatos CA) Nagasamy Vijay (Union City CA), Specification and design of complex digital systems.
  31. Brasen Daniel R. (San Francisco CA) Ashtaputre Sunil V. (San Jose CA), Symbolic routing guidance for wire networks in VLSI circuits.
  32. Taylor Brad (Oakland CA) Dowling Robert (Albany CA), System for compiling algorithmic language source code for implementation in programmable hardware.

이 특허를 인용한 특허 (5)

  1. Bhattacharya, Debashis; Boppana, Vamsi, Context-sensitive constraint driven uniquification and characterization of standard cells.
  2. Potemski, Andrew Stanley; Tyson, John Scott, Method and apparatus for accelerating project start and tape-out.
  3. Singh,Deshanand P.; Brown,Stephen D.; Borer,Terry P.; Sanford,Chris; Quan,Gabriel, Method and apparatus for placement of components onto programmable logic devices.
  4. Van Ginneken, Lukas P. P. P.; Groeneveld, Patrick R.; Philipsen, Wilhelmus J. M., Method for storing multiple levels of design data in a common database.
  5. Van Antwerpen, Babette; Yuan, Jinyong; Karchmer, David, User-directed timing-driven synthesis.
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