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[미국특허] Method for programming complex PLD having more than one function block type 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-093/02
출원번호 US-0818138 (1997-03-12)
발명자 / 주소
  • Harrison David A.
  • Silver Joshua M.
  • Soe Soren T.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Bever
인용정보 피인용 횟수 : 152  인용 특허 : 21

초록 ▼

A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing bo

대표청구항 ▼

[ We claim:] [1.] A computer implemented method for configuring a programmable logic device to implement a logic function, the programmable logic device including a first type of function block and a second type of function block the method comprising the steps of:mapping portions of the logic funct

이 특허에 인용된 특허 (21) 인용/피인용 타임라인 분석

  1. Schmitz Nicholas A. (Cupertino CA), Apparatus and method for allocation of resoures in programmable logic devices.
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  2. Agrawal Om P. (Los Altos CA) Moench Jerry D. (Austin TX) Ilgenstein Kerry A. (Austin TX), Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices.
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  3. Chiang David (Saratoga CA), EPLD chip with hybrid architecture optimized for both speed and flexibility.
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  6. Agrawal Om P. (Los Altos CA) Ilgenstein Kerry A. (Austin TX), Flexible synchronous/asynchronous cell structure for a high density programmable logic device.
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  10. Knapp Steven K. (Santa Clara CA) Seidel Jorge P. (San Jose CA) Kelem Steven H. (Los Altos Hills CA), Method for generating logic modules from a high level block diagram.
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  11. Harrison David A. (Cupertino CA) Silver Joshua M. (Sunnyvale CA) Soe Soren T. (San Jose CA), Method for programming complex PLD having more than one function block type.
    상세보기
  12. Kamejima Shigehiro (Ome JPX) Hagiwara Yoshimune (Hachioji JPX) Noguchi Kouki (Kokubunji JPX) Ishii Minoru (Inagi JPX) Nishimukai Tadahiko (Sagamihara JPX) Nakamura Hideo (Tokyo JPX) Koizumi Haruo (To, Microprocessor chip using two-level metal lines technology.
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  13. Agrawal Om P. (San Jose CA) Landers George H. (Mountain View CA) Schmitz Nicholas A. (Cupertino CA) Moench Jerry D. (Austin TX) Ilgenstein Kerry A. (Austin TX), Multiple array high performance programmable logic device family.
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  14. Kondou Harufusa (Hyogo JPX) Kuranaga Hiroshi (Hyogo JPX), Programmable logic array having a changeable logic structure.
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