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Microelectronic packaging using arched solder columns 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
  • H01L-021/50
출원번호 US-0096754 (1998-06-12)
발명자 / 주소
  • Rinne Glenn A.
  • Deane Philip A.
출원인 / 주소
  • MCNC
대리인 / 주소
    Alston & Bird LLP
인용정보 피인용 횟수 : 62  인용 특허 : 35

초록 ▼

Microelectronic packages are formed wherein solder bumps on one or more substrates are expanded, to thereby extend and contact the second substrate and form a solder connection. The solder bumps are preferably expanded by reflowing additional solder into the plurality of solder bumps. The additional

대표청구항 ▼

[ That which is claimed:] [1.] A method of forming a microelectronic package comprising the steps of:orienting a first microelectronic substrate relative to a second microelectronic substrate, such that an edge of said second microelectronic substrate is adjacent said first microelectronic substrate

이 특허에 인용된 특허 (35)

  1. Walters Richard (58 Leandre St. Manchester NH 03102), Adjustable printed circuit board rack for supporting printed circuit boards in a horizontal or a vertical position.
    상세보기
  2. Hileman Vince (San Jose CA) Kitlas Kenneth (San Jose CA) Willis Clifford B. (Tracy CA), Card guide with groove having a base portion and ramped portion which restrains an electronic card.
    상세보기
  3. Sunstein Drew E. (310 Wheeler Rd. ; R.F.D. 6 Nashua NH 03060), Circuit board mounting device and associated components.
    상세보기
  4. Amano Toshiaki (Hiratsuka JPX) Hikasa Kazuhito (Hiratsuka JPX) Kumamoto Seishi (Kakogawa JPX) Fujiwara Takahiro (Ono JPX), Circuit board to be precoated with solder layers and solder circuit board.
    상세보기
  5. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  6. Carson John C. (Corona del Mar CA) Some Raphael R. (Irvine CA), Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack.
    상세보기
  7. Pepe Angel A. (Irvine CA) Reinker David M. (Rancho Santa Margarita CA) Minahan Joseph A. (Simi Valley CA), Fabrication of dense parallel solder bump connections.
    상세보기
  8. Wheeler Richard L. (San Jose CA) Nagesh Voddarahalli K. (Cupertino CA), High-speed, high-density chip mounting.
    상세보기
  9. Butler Peter O. ; Suarez-Gartner Ricardo E., Method and apparatus for reducing warpage of an assembly substrate.
    상세보기
  10. Kondo Kenji (Hoi JPX) Kunda Hachiro (Chiryu JPX) Sonobe Toshio (Okazaki JPX), Method for making a semiconductor device.
    상세보기
  11. Dishon Giora J. (Chapel Hill NC), Method of building solder bumps.
    상세보기
  12. Kitayama Yoshifumi,JPX ; Mori Kazuhiro,JPX ; Saeki Keiji,JPX ; Akiguchi Takashi,JPX, Method of packaging electronic chip component and method of bonding of electrode thereof.
    상세보기
  13. Cayetano Jos (Chaville FRX) Lemasson Alain (Sevres FRX) Mur Rmy (Montrouge FRX), Method of wiring between package outputs and hybrid elements.
    상세보기
  14. Del Monte ; Louis A., Microcircuit device metallization.
    상세보기
  15. Carson John C. (Corona del Mar CA) Indin Ronald J. (Huntington Beach CA) Shanken Stuart N. (Irvine CA), Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip.
    상세보기
  16. Eichelberger Charles W. (Schenectady NY), Multichip integrated circuit modules.
    상세보기
  17. Miyake Michael K. (Westminster CA), Non-conductive end layer for integrated stack of IC chips.
    상세보기
  18. Newmark Martin (P.O. Box 1338 Boulder CO 80306), Organizational display for compact disc jewel boxes.
    상세보기
  19. Malhi Satwinder (Garland TX) Bean Kenneth E. (Celina TX) Driscoll Charles C. (Richardson TX) Chatterjee Pallab K. (Dallas TX), Orthogonal chip mount system module and method.
    상세보기
  20. Welsch, John H., Panels for holding printed circuit boards.
    상세보기
  21. Reimer William A. (Wheaton IL), Printed wiring board file and method of utilizing the same.
    상세보기
  22. Kawakita Tetuo,JPX ; Hatada Kenzo,JPX, Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step.
    상세보기
  23. Heitzmann Michel (Crolles FRX) Lajzerowicz Jean (Meylan FRX) LaPorte Philippe (Sassenage FRX), Process for etching and depositing integrated circuit interconnections and contacts.
    상세보기
  24. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
    상세보기
  25. Gelsing Richardus Johannes Henricus (Eindhoven NL) VAN Steensel Kees (Eindhoven NL), Semiconductor device with multi-layered metal interconnections.
    상세보기
  26. Ishikawa Toshimitsu (Kawaguchi JPX) Kitamura Atsushi (Tokyo JPX) Hirayama Kenji (Ooita JPX), Semiconductor integrated circuit devices having particular terminal geometry.
    상세보기
  27. Yung Edward K. (Carrboro NC), Solder bump fabrication method.
    상세보기
  28. Yung Edward K. (Carrboro NC), Solder bump including circular lip.
    상세보기
  29. Moore Kevin D. (Schaumburg IL) Missele Carl (Elgin IL), Solder bumping of integrated circuit die.
    상세보기
  30. Moore Kevin D. (Schaumburg IL) Stafford John W. (St. Charles IL) Beckenbaugh William M. (Barrington IL) Cholewczynski Ken (Streamwood IL), Solder plate reflow method for forming a solder bump on a circuit trace intersection.
    상세보기
  31. Moore Kevin D. (Schaumburg) Stafford John W. (St. Charles) Beckenbaugh William M. (Barrington) Cholewczynski Ken (Streamwood IL), Solder plate reflow method for forming solder-bumped terminals.
    상세보기
  32. Cotues Paul W. (Yorktown Heights NY) Moskowitz Paul A. (Yorktown Heights NY) Murphy Philip (New Fairfield CT) Ritter Mark B. (Brookfield CT) Walker George F. (New York NY), Stepped electronic device package.
    상세보기
  33. Chizen Dwight (403 Sackville St. Toronto ; Ontario CAX M4X 1S6), Storage rack for cassettes and compact discs.
    상세보기
  34. Frew Dean L. (Garland TX) Kressley Mark A. (Richardson TX) Wilson Arthur M. (Richardson TX) Miller Juanita G. (Richardson TX) Hecker ; Jr. Philip E. (Garland TX) Drumm James (Crystal Lake IL) Johnson, Three dimensional assembly of integrated circuit chips.
    상세보기
  35. Pedder David J. (Oxon GB3), Vernier structure for flip chip bonded devices.
    상세보기

이 특허를 인용한 특허 (62)

  1. Baleras, François; Souriau, Jean-Charles; Poupon, Gilles; Verrun, Sophie, 3D integration of vertical components in reconstituted substrates.
    상세보기
  2. Trezza, John, Back-to-front via process.
    상세보기
  3. Trezza, John, Chip capacitive coupling.
    상세보기
  4. Trezza, John, Chip capacitive coupling.
    상세보기
  5. Trezza, John; Callahan, John; Dudoff, Gregory, Chip connector.
    상세보기
  6. Trezza, John, Chip spanning connection.
    상세보기
  7. Trezza, John, Chip-based thermo-stack.
    상세보기
  8. Trezza, John, Chip-based thermo-stack.
    상세보기
  9. Trezza, John, Coaxial through chip connection.
    상세보기
  10. Trezza, John; Callahan, John; Dudoff, Gregory, Contact-based encapsulation.
    상세보기
  11. Trezza, John, Electrically conductive interconnect system and method.
    상세보기
  12. Trezza, John; Callahan, John; Dudoff, Gregory, Electronic chip contact structure.
    상세보기
  13. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
    상세보기
  14. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
    상세보기
  15. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
    상세보기
  16. Trezza, John, Front-end processed wafer having through-chip connections.
    상세보기
  17. Kim, DaeSup; Kim, YoungJoon; Choi, DaeSik, Integrated circuit packaging system with chip stacking and method of manufacture thereof.
    상세보기
  18. Trezza, John, Inverse chip connector.
    상세보기
  19. Trezza, John, Inverse chip connector.
    상세보기
  20. Trezza, John, Isolating chip-to-chip contact.
    상세보기
  21. Trezza, John, Isolating chip-to-chip contact.
    상세보기
  22. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
    상세보기
  23. Haim Feigenbaum ; Chris M. Schreiber, Method for joining an integrated circuit.
    상세보기
  24. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  25. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  26. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
    상세보기
  27. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
    상세보기
  28. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
    상세보기
  29. Rinne,Glenn A., Methods of providing solder structures for out plane connections.
    상세보기
  30. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
    상세보기
  31. Glenn A. Rinne, Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles.
    상세보기
  32. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
    상세보기
  33. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
    상세보기
  34. Trezza, John; Callahan, John; Dudoff, Gregory, Patterned contact.
    상세보기
  35. Trezza, John; Frushour, Ross, Pin-type chip tooling.
    상세보기
  36. Trezza, John, Plated pillar package formation.
    상세보기
  37. Trezza, John; Callahan, John; Dudoff, Gregory, Post & penetration interconnection.
    상세보기
  38. Trezza, John, Post-attachment chip-to-chip connection.
    상세보기
  39. Trezza, John, Process for chip capacitive coupling.
    상세보기
  40. Oppermann,Hans Hermann; Zakel,Elke; Azdasht,Ghassem; Kasulke,Paul, Process for the formation of a spatial chip arrangement and spatial chip arrangement.
    상세보기
  41. Trezza, John, Processed wafer via.
    상세보기
  42. Trezza, John, Processed wafer via.
    상세보기
  43. Trezza, John; Callahan, John; Dudoff, Gregory, Profiled contact.
    상세보기
  44. Hall, Douglas C.; Howard, Scott; Hoffman, Anthony; Bernstein, Gary H.; Kulick, Jason M., Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment.
    상세보기
  45. Van Veen, Nicolaas Johannes Anthonius; Goshen, Rafael; Yogev, David; Livne, Amir, Radiation detector element.
    상세보기
  46. Trezza, John, Redundant optical device array.
    상세보기
  47. Trezza, John, Remote chip attachment.
    상세보기
  48. Trezza, John, Remote chip attachment.
    상세보기
  49. Trezza, John; Frushour, Ross, Rigid-backed, membrane-based chip tooling.
    상세보기
  50. Misra, Abhay; Trezza, John, Routingless chip architecture.
    상세보기
  51. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  52. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  53. Trezza, John, Side stacking apparatus and method.
    상세보기
  54. Deane,Philip; Teitelbaum,Neil, Solder bonding technique for assembling a tilted chip or substrate.
    상세보기
  55. Rinne, Glenn A., Solder structures for out of plane connections.
    상세보기
  56. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
    상세보기
  57. Rinne,Glenn A., Stacked electronic structures including offset substrates.
    상세보기
  58. Trezza, John, Thermally balanced via.
    상세보기
  59. Trezza,John, Through chip connection.
    상세보기
  60. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.
    상세보기
  61. Trezza, John, Triaxial through-chip connection.
    상세보기
  62. Trezza, John, Triaxial through-chip connection.
    상세보기

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