초록 ▼

The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present

The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint. However, in a more advantageous embodiment, the bond pad footprint overlays a substantial portion of the metal layer footprint and the BIST footprint.

대표청구항 ▼

[ What is claimed is:] [1.] An integrated circuit having a substrate and active devices formed on the surface of said substrate and comprising:a bond pad formed over a portion of said active devices and having a bond pad footprint;a patterned metal layer having a metal layer footprint and located be

[ What is claimed is:] [1.] An integrated circuit having a substrate and active devices formed on the surface of said substrate and comprising:a bond pad formed over a portion of said active devices and having a bond pad footprint;a patterned metal layer having a metal layer footprint and located between said bond pad and said substrate; anda built-in self-test (BIST) circuit having a BIST footprint and located between said substrate and said bond pad, said bond pad footprint overlaying at least a portion of said metal layer footprint and said BIST footprint.