초록 ▼

A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists

A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.

대표청구항 ▼

[ We claim:] [1.] A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising:a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin,

[ We claim:] [1.] A system for controlling registers associated with non-volatile elements of configuration bits in a programmable logic device comprising:a boundary scan test circuit including a number of external device pins, one of the external device pins being defined as a test data input pin, and at least one test data register which is defined as a configuration register;a set of serially connected configuration bit non-volatile element sense latches (CBSLs), the CBSLs storing a set of data of the non-volatile elements;means for processing the set of data of the non-volatile elements from the CBSLs to the configuration register when a first signal is applied; andmeans for processing a set of test data signals from the test data input pin to the configuration register when a second signal is applied.