$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Single in-line memory module 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-013/00
출원번호 US-0878705 (1997-06-19)
발명자 / 주소
  • Bechtolsheim Andreas
  • Frank Edward
  • Testa James
  • Storm Shawn
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Conley, Rose & Tayon, PCKivlin
인용정보 피인용 횟수 : 180  인용 특허 : 82

초록 ▼

A single in-line memory module (SIMM) for memory expansion in a computer system. The SIMM includes a plurality of memory chips surface-mounted on a printed circuit board. The printed circuit board includes a dual read-out connector edge adapted for insertion within a socket of the computer system. O

대표청구항 ▼

[ We claim:] [1.] A single in-line memory module for memory expansion in a computer system, the single in-line memory module comprising:a printed circuit board having a first side and a second side, wherein the printed circuit board includes a connector edge adapted for insertion within a socket of

이 특허에 인용된 특허 (82) 인용/피인용 타임라인 분석

  1. Hargis Billy M. (Hugo MN), Array of electronic packaging substrates.
    상세보기
  2. Testa James (Mountain View CA) Behtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Creary Trevor (Mountain View CA) Emberson David (Santa Cruz CA) Storm Shawn F. (Mountain Valley CA) H, Bus architecture for integrated data and video memory.
    상세보기
  3. Verhoeven Laurentius M. (Veghel NLX) van Nes Cornelis G. J. (Oisterwijk NLX), Card holder.
    상세보기
  4. Blake Bruce E. (LaGrangeville NY) Hultmark Eric B. (Wappingers Falls NY) Presti Frank P. (Hopewell Junction NY) Ricci Raymond (Wappingers Falls NY) Rippens Roger A. (Salt Point NY), Ceramic card assembly having enhanced power distribution and cooling.
    상세보기
  5. Cobaugh ; Robert Franklin ; Coller ; James Ray, Circuit board connector.
    상세보기
  6. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC), Circuit panel socket with cloverleaf contact.
    상세보기
  7. Yeung Tak-Kin (City One HKX), Combo SIMM connector.
    상세보기
  8. Bluethman Robert G. (Austin TX) Willson Donald J. (Leander TX), Computer memory module.
    상세보기
  9. Clayton James E. (Derry NH) Shamash Hooshang (Chelmsford MA), Connecting apparatus for electrically connecting memory modules to a printed circuit board.
    상세보기
  10. Saito Masaaki (Tokyo JPX), Connector for a printed circuit board.
    상세보기
  11. Corbett Tim J. (Boise ID) Wood Alan G. (Boise ID), Directly bonded board multiple integrated circuit module.
    상세보기
  12. Corbett Tim J. (Boise ID) Wood Alan G. (Boise ID), Directly bonded simm module.
    상세보기
  13. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC), Dual read-out SIMM socket for high electrical speed applications.
    상세보기
  14. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC), Dual readout SIMM socket.
    상세보기
  15. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC), Dual readout extended socket.
    상세보기
  16. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC) Zutaut Donald J. (Winston-Salem NC), Dual row connector for low profile package.
    상세보기
  17. Choy Conrad Y. (San Francisco CA) Yu Jack (Sunnyvale CA), Durable latch for memory module board.
    상세보기
  18. Yang Lee Su-Lan (4th Floor ; No. 506-2 ; Yuan-San Road Chung-Ho City ; Taipei Hsien TWX), Durable latch with mounting peg of memory module socket.
    상세보기
  19. Coller, James R.; Thrush, Roger L., Edge connector for chip carrier.
    상세보기
  20. Long Frank T. (1351 Rambling Rd. Simi Valley CA 93065), Ejecting SIMM socket.
    상세보기
  21. Billman Timothy B. (King NC) Thrush Roger L. (Clemmons NC), Electrical connector with module extraction apparatus.
    상세보기
  22. McGinley William J. (Barrington IL), Electrical edge connector.
    상세보기
  23. Krehbiel Fred L. (Lake Forest IL), Electrical socket assembly for single in-line circuit package.
    상세보기
  24. Angleton Joseph L. (Canoga Park CA) Gutgsell Jeffery L. (Simi Valley CA), Gate array with bidirectional symmetry.
    상세보기
  25. Tasch ; Jr. Aloysious F. (Richardson TX), High capacity dynamic ram cell.
    상세보기
  26. Wu Andrew L. (Shrewsbury) Smelser Donald W. (Bolton) Bruce ; II E. William (Lunenburg MA) O\Dea John (Galway IRX), High density memory array packaging.
    상세보기
  27. Alexander David (Mountain View CA) Anderson Michael E. (Sunnyvale CA) Bahr Richard G. (Menlo Park CA) Deneroff Martin M. (Palo Alto CA) Venkatasubramaniam Kumar (San Jose CA), High memory capacity DRAM SIMM.
    상세보기
  28. Testa James (Mountain View CA), High speed electrical signal interconnect structure.
    상세보기
  29. Wu Andrew L. (Shrewsbury MA) DaCosta Derrick D. (Fraimingham MA) Coe Stephen R. (Aushburnham MA) Pierce Donald C. (Fitchburg MA) Bruce ; II E. William (Luenenburg MA), High-density double-sided multi-string memory module with resistor for insertion detection.
    상세보기
  30. Ellis Wayne F. (Jericho VT) Klink Erich (Schoenaich DEX) Najmann Knut (Gaertringen DEX), Input signal redriver for semiconductor modules.
    상세보기
  31. Adachi Takao (Tokyo JPX), Integrated circuit having wiring strips for propagating in-phase signals.
    상세보기
  32. Fortuna Jon A. (Mechanicsburg PA), Integrated circuit module connector assembly.
    상세보기
  33. Penzel Hans-Joerg (Wolfratshausen DEX), Integrated memory module having selectable operating functions.
    상세보기
  34. Kajimoto Takeshi (Tokyo JPX) Kobayashi Mitsuteru (Saitama JPX) Sato Katsuyuki (Tokyo JPX) Shimbo Yutaka (Tokyo JPX), Large-scale semiconductor integrated circuit device and method for relieving the faults thereof.
    상세보기
  35. Kawai Hideki (Nara JPX) Fujii Masaru (Takatsuki JPX) Ohta Kiyoto (Takatsuki JPX) Maeyama Yoshikazu (Kyoto JPX), Layout for stable high speed semiconductor memory device.
    상세보기
  36. Noschese Rocco J. (Wilton CT), Low insertion force circuit board connector assembly.
    상세보기
  37. Billman Timothy B. (King NC) McHugh Robert G. (Lewisville NC) Thrush Roger L. (Clemmons NC), Low insertion force circuit panel socket.
    상세보기
  38. Georgopulos ; Thomas, Low insertion force connector.
    상세보기
  39. Takeda Takashi (Tokyo JPX) Ushida Youichi (Tokyo JPX), Memory module.
    상세보기
  40. Neal Joseph H. (Missouri City TX) Poteet Kenneth A. (Houston TX), Memory module arranged for data and parity bits.
    상세보기
  41. Protigal Stanley N. (Boise ID) Chern Web-Foo (Boise ID) Parkinson Ward D. (Boise ID) Nevill Leland R. (Boise ID) Johnson Gary M. (Boise ID) Trent Thomas M. (Boise ID) Duesman Kevin G. (Boise ID), Memory module having on-chip surge capacitors.
    상세보기
  42. Walkup William B. (Barrington RI) D\Amico Richard J. (Cranston RI), Memory module socket.
    상세보기
  43. Bakke Patrick D. (Naperville IL) DiViesti Anthony M. (Park Ridge IL) Regnier Kent E. (Lombard IL) Yagi Masanori (Sagamihara JPX) Yamada Shoji (Adachi IL JPX) Walse Alan (LaGrange IL), Metal latch for SIMM socket.
    상세보기
  44. Bakke Patrick D. (Naperville IL) DiViesti Anthony M. (Park Ridge IL) Regnier Kent E. (Lombard IL) Yagi Masanori (Sagamihara JPX) Yamada Shoji (Adachi IL JPX) Walse Alan (LaGrange IL), Metal latch for SIMM socket.
    상세보기
  45. Davis ; Jr. Donald J. (Rocky Point NY) Insetta Victor (Jacksonville FL), Miniature monolithic ceramic coupler for electronic circuits.
    상세보기
  46. Windsor James A. (Tomball TX) Hamid Mustafa A. (Houston TX) Thoma Roy E. (Houston TX) Paschal James P. (Spring TX) Felcman Francis A. (Rosenberg TX), Modular computer memory circuit board.
    상세보기
  47. Ohno Kenichi (Tokyo JPX) Hosomizu Tohru (Yokohama JPX) Ogawa Rokutaro (Tokyo JPX), Multilevel masterslice LSI with second metal level programming.
    상세보기
  48. Hvezda Jaroslav M. (Nepean CAX) Velsher Benne (Ottawa CAX) Middlehurst Richard J. (Kanata CAX), Multiple contact connector having a low insertion force.
    상세보기
  49. Hamsher ; Jr. Wilbur A. (Carlisle PA) Weber Robert N. (Hummelstown PA), One piece zif connector.
    상세보기
  50. Wood Alan G. (Boise ID) Corbett Tim J. (Boise ID), Packaging for semiconductor logic devices.
    상세보기
  51. Anzelone Thomas A. (Ft. Lauderdale FL) Cheung Samuel T. (Boca Raton FL) Cohen Mark E. (Boca Raton FL) Cooke Kevin K. (Delray Beach FL) Dewitt John R. (Boca Raton FL) Miller Michael S. (Delray Beach F, Personal computer processor card interconnect system.
    상세보기
  52. Durkos Larry G. (Lebanon IN) Taylor Duaine O. (Carmel IN) Franklin Timothy E. (Zionsville IN), Portable computer.
    상세보기
  53. Robertson, John A., Printed circuit board edge connectors.
    상세보기
  54. DePaul Albert D. (413 W. 52nd St. New York NY 10019), Printed circuits.
    상세보기
  55. Hawkins George W. (Mesa AZ), Rail bonded multi-chip leadframe, method and package.
    상세보기
  56. Toshio Sugano (Kokubunji JPX) Seiichirou Tsukui (Komoro JPX) Shigeru Suzuki (Kokubunji JPX), Semiconductor device.
    상세보기
  57. Uemura Shunichi (Itami JPX) Murasawa Yashuhiro (Itami JPX), Semiconductor device.
    상세보기
  58. Arakawa Ryutaro (Ibaraki JPX) Fukutake Sunao (Ibaraki JPX), Semiconductor device and the manufacture thereof.
    상세보기
  59. Akasaki Hidehiko (Aizuwakamatsu JPX) Tsujimura Takehisa (Kawasaki JPX), Semiconductor device including leadless packages and a base plate for mounting the leadless packages.
    상세보기
  60. Sudo Toshio (Kawasaki JPX) Saito Kazutaka (Kawasaki JPX) Takubo Chiaki (Yokohama JPX), Semiconductor integrated circuit apparatus.
    상세보기
  61. Ohsawa Takashi (Kawasaki JPX), Semiconductor memory device.
    상세보기
  62. Sasaki Nobuo (Kawasaki JPX) Kobayashi Yasuo (Kawasaki JPX) Iwai Takashi (Kawasaki JPX) Nakano Motoo (Yokohama JPX), Semiconductor memory device.
    상세보기
  63. Takagi Yuichi (Kanagawa JPX), Semiconductor memory module.
    상세보기
  64. Kosugi Ryuichi (Hyogo JPX) Tabaru Tsugio (Hyogo JPX), Semiconductor pseudo memory module.
    상세보기
  65. Johnson Gary M. (Boise ID) Nevill Leland R. (Boise ID), Short-resistant decoupling capacitor system for semiconductor circuits.
    상세보기
  66. Clayton James E. (Londonderry NH), Signal in-line memory module.
    상세보기
  67. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
    상세보기
  68. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
    상세보기
  69. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
    상세보기
  70. Clayton James E. (Londonderry NH), Single in-line memory module.
    상세보기
  71. Schmidt Robert W. (Stafford TX), Sixteen bit microcomputer memory boards for use with eight bit standard connector bus.
    상세보기
  72. Thrush Roger L. (Clemmons NC), Socket for single in-line memory module.
    상세보기
  73. Kane Milburn H. (Austin TX) Roby John G. (Cedar Park TX) Schrottke Gustav (Austin TX), Stacked DCA memory chips.
    상세보기
  74. Mueller Wolfgang R. (Wappingers Falls NY) Spencer ; II Gwynne W. (Poughkeepsie NY), Stacked double density memory module using industry standard memory chips.
    상세보기
  75. Shaffer James M. (Boise) Mauritz Karl H. (Boise) Atkins Glen (Boise ID), Stacked printed circuit board device.
    상세보기
  76. Quattrini Victor L. (Westford MA) Fisher Edwin P. (Abington MA), Surface mounted multilayer memory printed circuit board.
    상세보기
  77. Mauritz Karl H. (Eagle ID) Leger Geary L. (Boise ID) Wicklund Joseph B. (Bothell WA) Herrud James E. (Boise ID) Laney Steven H. (Boise ID), Switched memory module.
    상세보기
  78. Iwamatsu Seiichi (Suwa JPX), Thin film metal interconnects in integrated circuit structures to reduce circuit operation speed delay.
    상세보기
  79. Hong Gary (Hsinchu TWX), Ulsi mask ROM structure and method of manufacture.
    상세보기
  80. Henle Robert A. (Clinton Corners NY) Johnson Alfred H. (Poughkeepsie NY), Vertical semiconductor integrated circuit chip packaging.
    상세보기
  81. Anhalt John W. (Orange CA) Curley James H. (Costa Mesa CA), Zero force printed circuit board connector.
    상세보기
  82. Grabbe Dimitry (Middletown PA) Korsunsky Iosif (Harrisburg PA) Klunk Thomas M. (Dover PA) DiOrazio Joseph S. (Harrisburg PA), Zero insertion force connector having wiping action.
    상세보기

이 특허를 인용한 특허 (180) 인용/피인용 타임라인 분석

  1. Dreps,Daniel M.; Ferriaolo,Frank D.; Gower,Kevin C.; Kellogg,Mark W.; Rippens,Roger A., 276-Pin buffered memory module with enhanced fault tolerance.
    상세보기
  2. Larson, Douglas A.; Cronin, Jeffrey J, Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
    상세보기
  3. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
    상세보기
  4. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
    상세보기
  5. Larson, Douglas A.; Cronin, Jeffrey J., Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system.
    상세보기
  6. Jeddeloh, Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
    상세보기
  7. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
    상세보기
  8. Jeddeloh,Joseph M., Apparatus and method for direct memory access in a hub-based memory system.
    상세보기
  9. Radke,William; Peterson,James R., Apparatus and method for distributed memory control in a graphics processing system.
    상세보기
  10. Lee, Terry R.; Jeddeloh, Joseph, Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules.
    상세보기
  11. Lee, Terry R.; Jeddeloh, Joseph M., Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules.
    상세보기
  12. Lee, Terry R.; Jeddeloh, Joseph M., Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules.
    상세보기
  13. Lee,Terry R.; Jeddeloh,Joseph M., Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules.
    상세보기
  14. Lee,Terry R.; Jeddeloh,Joseph M., Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules.
    상세보기
  15. Meyer, James W.; Kanski, Cory, Arbitration system and method for memory responses in a hub-based memory system.
    상세보기
  16. Meyer,James W.; Kanski,Cory, Arbitration system and method for memory responses in a hub-based memory system.
    상세보기
  17. Bhakta, Jayesh R.; Pauley, Jr., Robert S., Arrangement of integrated circuits in a memory module.
    상세보기
  18. Bhakta, Jayesh R.; Pauley, Jr., Robert S., Arrangement of integrated circuits in a memory module.
    상세보기
  19. Bhakta, Jayesh R.; Pauley, Jr., Robert S., Arrangement of integrated circuits in a memory module.
    상세보기
  20. Bhakta, Jayesh R.; Pauley, Jr., Robert S., Arrangement of integrated circuits in a memory module.
    상세보기
  21. Jeddeloh, Joseph, Buffer control system and method for a memory system having outstanding read and write request buffers.
    상세보기
  22. Jeddeloh, Joseph M., Buffer control system and method for a memory system having outstanding read and write request buffers.
    상세보기
  23. Jeddeloh,Joseph M., Buffer control system and method for a memory system having outstanding read and write request buffers.
    상세보기
  24. Tremaine, Robert B., Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables.
    상세보기
  25. LaBerge, Paul A., Delay line synchronizer apparatus and method.
    상세보기
  26. LaBerge, Paul A., Delay line synchronizer apparatus and method.
    상세보기
  27. LaBerge, Paul A., Delay line synchronizer apparatus and method.
    상세보기
  28. Tremaine,Robert B., Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables.
    상세보기
  29. LaBerge, Paul A., Dynamic command and/or address mirroring system and method for memory modules.
    상세보기
  30. LaBerge,Paul A., Dynamic command and/or address mirroring system and method for memory modules.
    상세보기
  31. Hazelzet,Bruce G., High density high reliability memory module with a fault tolerant address and command bus.
    상세보기
  32. Hazelzet, Bruce G., High density high reliability memory module with power gating and a fault tolerant address and command bus.
    상세보기
  33. Jeddeloh, Joseph M.; James, Ralph, Memory arbitration system and method having an arbitration packet protocol.
    상세보기
  34. Jeddeloh, Joseph M.; James, Ralph, Memory arbitration system and method having an arbitration packet protocol.
    상세보기
  35. Jeddeloh,Joseph M.; James,Ralph, Memory arbitration system and method having an arbitration packet protocol.
    상세보기
  36. Jeddeloh,Joseph M.; James,Ralph, Memory arbitration system and method having an arbitration packet protocol.
    상세보기
  37. Zimmerman,David, Memory channel test fixture and method.
    상세보기
  38. Park, Chul-woo; Jun, Young-hyun; Choi, Joo-sun; Hwang, Hong-sun, Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same.
    상세보기
  39. Kadota, Daisuke, Memory control circuit in a memory chip.
    상세보기
  40. Jeddeloh, Joseph M., Memory hub and access method having a sequencer and internal row caching.
    상세보기
  41. Lee, Terry R.; Jeddeloh, Joseph, Memory hub and access method having internal prefetch buffers.
    상세보기
  42. Lee,Terry R.; Jeddeloh,Joseph, Memory hub and access method having internal prefetch buffers.
    상세보기
  43. Lee,Terry R.; Jeddeloh,Joseph M., Memory hub and access method having internal prefetch buffers.
    상세보기
  44. Jeddeloh,Joseph M., Memory hub and access method having internal row caching.
    상세보기
  45. Jeddeloh, Joseph M., Memory hub and method for memory sequencing.
    상세보기
  46. Jeddeloh,Joseph M., Memory hub and method for memory sequencing.
    상세보기
  47. Jeddeloh,Joseph M., Memory hub and method for memory sequencing.
    상세보기
  48. Jeddeloh,Joseph M., Memory hub and method for providing memory sequencing hints.
    상세보기
  49. Jeddeloh,Joseph M., Memory hub and method for providing memory sequencing hints.
    상세보기
  50. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
    상세보기
  51. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
    상세보기
  52. Jeddeloh, Joseph M., Memory hub bypass circuit and method.
    상세보기
  53. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
    상세보기
  54. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
    상세보기
  55. Jeddeloh,Joseph M., Memory hub bypass circuit and method.
    상세보기
  56. Jeddeloh, Joseph M., Memory hub tester interface and method for use thereof.
    상세보기
  57. Jeddeloh,Joseph M., Memory hub tester interface and method for use thereof.
    상세보기
  58. Schnepper, Randy L., Memory hub with integrated non-volatile memory.
    상세보기
  59. Schnepper, Randy L., Memory hub with integrated non-volatile memory.
    상세보기
  60. Schnepper,Randy L., Memory hub with integrated non-volatile memory.
    상세보기
  61. Schnepper,Randy L., Memory hub with integrated non-volatile memory.
    상세보기
  62. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
    상세보기
  63. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
    상세보기
  64. Jeddeloh, Joseph M., Memory hub with internal cache and/or memory access prediction.
    상세보기
  65. Jeddeloh,Joseph M., Memory hub with internal cache and/or memory access prediction.
    상세보기
  66. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
    상세보기
  67. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
    상세보기
  68. Pax, George E.; Greeff, Roy E., Memory module and method having improved signal routing topology.
    상세보기
  69. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
    상세보기
  70. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
    상세보기
  71. Pax,George E.; Greeff,Roy E., Memory module and method having improved signal routing topology.
    상세보기
  72. Verma, Vani; Chhor, Khushrav S., Memory module having interconnected and stacked integrated circuits.
    상세보기
  73. Verma,Vani; Chhor,Khushrav S., Memory module having interconnected and stacked integrated circuits.
    상세보기
  74. Verma,Vani; Chhor,Khushrav S., Memory module having interconnected and stacked integrated circuits.
    상세보기
  75. RaghuRam,Siva; Schuster,Josef; Muff,Simon; Bacha,Abdallah, Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type.
    상세보기
  76. Doblar, Drew G.; Ko, Han Y., Memory module with equal driver loading.
    상세보기
  77. Jeddeloh, Joseph M.; Lee, Terry R., Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules.
    상세보기
  78. Gower, Kevin C.; Kark, Kevin W.; Kellogg, Mark W.; Maule, Warren E., Memory subsystem with positional read data latency.
    상세보기
  79. James,Ralph, Method and system for capturing and bypassing memory transactions in a hub-based memory system.
    상세보기
  80. James,Ralph, Method and system for capturing and bypassing memory transactions in a hub-based memory system.
    상세보기
  81. Jeddeloh, Joseph M.; Lee, Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
    상세보기
  82. Jeddeloh,Joseph M.; Lee,Terry R., Method and system for controlling memory accesses to memory modules having a memory hub architecture.
    상세보기
  83. Coteus, Paul W.; Gower, Kevin C.; Maule, Warren E.; Tremaine, Robert B., Method and system for providing frame start indication in a memory system having indeterminate read data latency.
    상세보기
  84. Coteus, Paul W.; Gower, Kevin C.; Maule, Warren E.; Tremaine, Robert B., Method and system for providing identification tags in a memory system having indeterminate data response times.
    상세보기
  85. James, Ralph, Method and system for synchronizing communications links in a hub-based memory system.
    상세보기
  86. James,Ralph, Method and system for synchronizing communications links in a hub-based memory system.
    상세보기
  87. Cronin, Jeffrey J.; Larson, Douglas A., Method and system for terminating write commands in a hub-based memory system.
    상세보기
  88. Cronin,Jeffrey J.; Larson,Douglas A., Method and system for terminating write commands in a hub-based memory system.
    상세보기
  89. Gajewski,Michael W., Method for ensuring consistent protocol in the location of circuits and connectors having multiple circuit-receiving cavities.
    상세보기
  90. Tremaine, Robert B., Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables.
    상세보기
  91. Schulz, Jurgen, Module and connector having multiple contact rows.
    상세보기
  92. Chhor, Khushrav S.; Moresco, Larry L., Molded memory module and method of making the module absent a substrate support.
    상세보기
  93. Park, Sung-Joo; Ko, Ki-Hyun; Yun, Young; Kim, Soo-Kyung, Mounting structures for integrated circuit modules.
    상세보기
  94. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  95. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  96. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  97. Jeddeloh, Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  98. Jeddeloh,Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  99. Jeddeloh,Joseph M., Multiple processor system and method including multiple memory hub modules.
    상세보기
  100. Jeddeloh,Joseph M.; Lee,Terry R., Posted write buffers and methods of posting write requests in memory modules.
    상세보기
  101. Coteus, Paul W.; Gower, Kevin C.; Maule, Warren E.; Tremaine, Robert B., Providing frame start indication in a memory system having indeterminate read data latency.
    상세보기
  102. Coteus, Paul W.; Gower, Kevin C.; Maule, Warren E.; Tremaine, Robert B., Providing frame start indication in a memory system having indeterminate read data latency.
    상세보기
  103. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
    상세보기
  104. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
    상세보기
  105. Lee, Terry R.; Jeddeloh, Joseph M., Reconfigurable memory module and method.
    상세보기
  106. Lee,Terry R.; Jeddeloh,Joseph M., Reconfigurable memory module and method.
    상세보기
  107. Gower, Kevin C.; Maule, Warren E.; Saalmueller, Juergen, Service interface to a memory system.
    상세보기
  108. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
    상세보기
  109. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
    상세보기
  110. LaBerge, Paul A., System and method for an asynchronous data buffer having buffer write and read pointers.
    상세보기
  111. Jeddeloh,Joseph M., System and method for arbitration of memory responses in a hub-based memory system.
    상세보기
  112. James,Ralph, System and method for communicating the synchronization status of memory modules during initialization of the memory modules.
    상세보기
  113. James,Ralph, System and method for communicating the synchronization status of memory modules during initialization of the memory modules.
    상세보기
  114. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  115. Jeddeloh, Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  116. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  117. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  118. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  119. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  120. Jeddeloh,Joseph M., System and method for memory hub-based expansion bus.
    상세보기
  121. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
    상세보기
  122. Murphy,Tim, System and method for multiple bit optical data transmission in memory systems.
    상세보기
  123. Jeddeloh, Joseph M., System and method for on-board diagnostics of memory modules.
    상세보기
  124. Jeddeloh,Joseph M., System and method for on-board diagnostics of memory modules.
    상세보기
  125. Jeddeloh,Joseph M., System and method for on-board diagnostics of memory modules.
    상세보기
  126. Jeddeloh, Joseph M., System and method for on-board timing margin testing of memory modules.
    상세보기
  127. Jeddeloh,Joseph M., System and method for on-board timing margin testing of memory modules.
    상세보기
  128. Taylor,George R., System and method for optically interconnecting memory devices.
    상세보기
  129. Taylor,George R., System and method for optically interconnecting memory devices.
    상세보기
  130. Taylor,George R., System and method for optically interconnecting memory devices.
    상세보기
  131. Taylor,George R., System and method for optically interconnecting memory devices.
    상세보기
  132. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
    상세보기
  133. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
    상세보기
  134. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
    상세보기
  135. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
    상세보기
  136. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
    상세보기
  137. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
    상세보기
  138. Jeddeloh, Joseph M.; LaBerge, Paul, System and method for read synchronization of memory modules.
    상세보기
  139. Jeddeloh, Joseph M.; LaBerge, Paul A., System and method for read synchronization of memory modules.
    상세보기
  140. Jeddeloh,Joseph M.; LaBerge,Paul, System and method for read synchronization of memory modules.
    상세보기
  141. Jeddeloh,Joseph M.; LaBerge,Paul, System and method for read synchronization of memory modules.
    상세보기
  142. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
    상세보기
  143. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
    상세보기
  144. Jeddeloh,Joseph M.; Lee,Terry, System and method for selective memory module power management.
    상세보기
  145. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
    상세보기
  146. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
    상세보기
  147. James,Ralph; Jeddeloh,Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
    상세보기
  148. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  149. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  150. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
    상세보기
  151. Jeddeloh, Joseph M.; Lee, Terry R., System for controlling memory accesses to memory modules having a memory hub architecture.
    상세보기
  152. Gower, Kevin C.; Maule, Warren E., System, method and storage medium for a memory subsystem command interface.
    상세보기
  153. Gower,Kevin C.; Maule,Warren E., System, method and storage medium for a memory subsystem command interface.
    상세보기
  154. Gower, Kevin C.; Kellogg, Mark W., System, method and storage medium for a multi-mode memory buffer device.
    상세보기
  155. Gower,Kevin C.; Kellogg,Mark W., System, method and storage medium for a multi-mode memory buffer device.
    상세보기
  156. Ferraiolo, Frank D.; Gower, Kevin C., System, method and storage medium for bus calibration in a memory subsystem.
    상세보기
  157. Ferraiolo,Frank D.; Gower,Kevin C.; Schmatz,Martin L., System, method and storage medium for deriving clocks in a memory system.
    상세보기
  158. Cowell,Thomas M.; Gower,Kevin C.; LaPietra,Frank, System, method and storage medium for providing a high speed test interface to a memory subsystem.
    상세보기
  159. Gower, Kevin C.; Kark, Kevin W.; Kellogg, Mark W.; Maule, Warren E., System, method and storage medium for providing a serialized memory interface with a bus repeater.
    상세보기
  160. Gower,Kevin C.; Maule,Warren E.; Saalmueller,Juergen, System, method and storage medium for providing a service interface to a memory system.
    상세보기
  161. Gower,Kevin C.; Kellogg,Mark W.; Maule,Warren E.; Smith, III,Thomas B.; Tremaine,Robert B., System, method and storage medium for providing data caching and data compression in a memory subsystem.
    상세보기
  162. Gower,Kevin C.; Kellogg,Mark W.; Maule,Warren E.; Smith, III,Thomas B.; Tremaine,Robert B., System, method and storage medium for providing data caching and data compression in a memory subsystem.
    상세보기
  163. Gower,Kevin C.; Kellogg,Mark W.; Maule,Warren E.; Smith, III,Thomas B.; Tremaine,Robert B., System, method and storage medium for providing data caching and data compression in a memory subsystem.
    상세보기
  164. Dell, Timothy J.; Gower, Kevin C.; Maule, Warren E., System, method and storage medium for providing fault detection and correction in a memory subsystem.
    상세보기
  165. Dell, Timothy J.; Gower, Kevin C.; Maule, Warren E., System, method and storage medium for providing fault detection and correction in a memory subsystem.
    상세보기
  166. Dell,Timothy J.; Gower,Kevin C.; Maule,Warren E., System, method and storage medium for providing fault detection and correction in a memory subsystem.
    상세보기
  167. Dell, Timothy J.; Ferraiolo, Frank D.; Gower, Kevin C.; Kark, Kevin W.; Kellogg, Mark W.; Maule, Warren E., System, method and storage medium for providing segment level sparing.
    상세보기
  168. Cowell,Thomas M.; Ferraiolo,Frank D.; Gower,Kevin C.; LaPietra,Frank, System, method and storage medium for testing a memory module.
    상세보기
  169. Dell, Timothy J.; Lastras-Montano, Luis A., Systems and methods for improving serviceability of a memory system.
    상세보기
  170. Brittain, Mark A.; Maule, Warren E.; Rajamani, Karthick; Retter, Eric E.; Tremaine, Robert B., Systems and methods for memory module power management.
    상세보기
  171. Gower, Kevin C.; VanStee, Dustin J., Systems and methods for providing a dynamic memory bank page policy.
    상세보기
  172. Gower, Kevin C.; Griffin, Thomas J.; VanStee, Dustin J., Systems and methods for providing collision detection in a memory system.
    상세보기
  173. Tremaine, Robert B., Systems and methods for providing data modification operations in memory subsystems.
    상세보기
  174. Gower, Kevin C.; Tremaine, Robert B., Systems and methods for providing distributed autonomous power management in a memory system.
    상세보기
  175. Gower, Kevin C.; Maule, Warren E.; Tremaine, Robert B., Systems and methods for providing distributed technology independent memory controllers.
    상세보기
  176. VanStee, Dustin J.; Gower, Kevin C., Systems and methods for providing dynamic memory pre-fetch.
    상세보기
  177. Coteus, Paul W.; Maule, Warren E.; Seminaro, Edward J.; Tremaine, Robert B., Systems and methods for providing memory modules with multiple hub devices.
    상세보기
  178. Gower,Kevin C.; Love,Carl E.; VanStee,Dustin J., Systems and methods for providing performance monitoring in a memory system.
    상세보기
  179. Tremaine, Robert B., Systems and methods for providing remote pre-fetch buffers.
    상세보기
  180. Lee,Terry R.; Jeddeloh,Joseph M., Wavelength division multiplexed memory module, memory system and method.
    상세보기

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로