초록 ▼

The I-cell term representation is sufficiently broad in its scope to allow representation of sub-functions such as ABC+ABC as a single entity that can be readily used for minimization which may be advantageously used in logic circuit fabrication and design. Since I-cell representation includes sum o

The I-cell term representation is sufficiently broad in its scope to allow representation of sub-functions such as ABC+ABC as a single entity that can be readily used for minimization which may be advantageously used in logic circuit fabrication and design. Since I-cell representation includes sum of products, EXOR, EXNOR and other logic terms, fewer terms will be needed to represent a given Boolean function, and a much more simplified, inexpensive and advantageous optimal logic design structure will be obtained.

대표청구항 ▼

[ What we claim is:] [1.] A method to simplify a plurality of gates on a logic circuit, comprising the steps of:examining said logic circuit on a means for analyzing a circuit to form a circuit description describing said logic circuit mathematically as a plurality of logic terms, said logic circuit

[ What we claim is:] [1.] A method to simplify a plurality of gates on a logic circuit, comprising the steps of:examining said logic circuit on a means for analyzing a circuit to form a circuit description describing said logic circuit mathematically as a plurality of logic terms, said logic circuit being mathematically represented by a function f(.) as a sum of minterms, wherein the function f(.) of said logic circuit having a plurality of minterms and a plurality of input signal variables;defining a Set-1 of said plurality of minterms;defining all terms generated as a Set-2;defining said plurality of input signal variables by a variable n;defining a dummy variable i;initializing the value of said dummy variable i as i=1;generating a plurality of single identity cell terms by first selecting pairs of terms from said Set-1 having common variables and adding said pairs of terms together witb a sum forming one of said plurality of identity cell terms;adding all remaining variables from said Set-1 in true form in one term together with 1's complement form in another term with a result forming another one of said plurality of identity cell terms;marking each of said plurality of identity cell terms with a symbol;forming an identity-cell from said plurality of single identity cell terms, said identity-cell having at least two gates and at least two signal inputs;retaining said marked plurality of identity cell terms in said Set-1;transferring said identity-cell to said Set-2;transferring said plurality of unmarked Set-1 terms to said Set-2;identifying a plurality of equivalent terms in said Set-2 having two terms of said identity cell with identical minterm representation;identifying a plurality of duplicate terms in said Set-2 having any one of said plurality of identity cell terms with identical minterm representation as any other of said plurality of identity cell terms;deleting said plurality of equivalent terms and said plurality of duplicate terms from said Set-2;identifying said marked plurality of identity cell terms in Set-1 with a value less than said variable n;identifying Set-1 terms where said i is a value less than said variable n;renaming said Set-2 as a second Set-1;redefining said Set-2 as a null set;obtaining a second Set-1 result, said second Set-1 result being a plurality of logic function f identity cells;representing a simplified plurality of gates for said logic circuit based on said plurality of logic function f identity cells; andconfiguring said logic circuit to operate with said simplified plurality of gates.