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Circuit and method for measuring and forcing an internal voltage of an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 US-0607688 (1996-02-27)
발명자 / 주소
  • Loughmiller Daniel R.
  • Sher Joseph C.
  • Duesman Kevin G.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg Woessner & Kluth P.A.
인용정보 피인용 횟수 : 67  인용 특허 : 17

초록

A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one version, the circuit (110) involves a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node

대표청구항

[ What is claimed is:] [1.] A circuit for reading a voltage at a node of an integrated circuit, the circuit comprising:a pass circuit coupled between the node of the integrated circuit and a pin of the integrated circuit;a reset circuit coupled to the pass circuit and operable to activate and reset

이 특허에 인용된 특허 (17)

  1. Lee Nai-Chi (Peekskill NY), Analog autonomous test bus framework for testing integrated circuits on a printed circuit board.
  2. Habersetzer Daryl L. (Boise ID) Kurth Casey R. (Boise ID) Mullarkey Patrick J. (Meridian ID) Graalum Jason E. (Boise ID), Apparatus for disabling and re-enabling access to IC test functions.
  3. Haulin Tord (Uppsala SEX), Device for monitoring the supply voltage on integrated circuits.
  4. Tanksalvala Darius F. (Denver CO) Quarnstrom Douglas A. (Fort Collins CO), Diagnostic system for integrated circuits using existing pads.
  5. Bhuva Rohit L. (Plano TX) Tran Bao (Richardson TX) Conner James L. (Rowlett TX) Overlaur Michael (Plano TX) Paulsen Tracy S. (Rowlett TX), Large integrated circuit with modular probe structures.
  6. Goel Prabhakar (Poughkeepsie NY) McMahon Maurice T. (Poughkeepsie NY), Method of electrically testing a packaging structure having N interconnected integrated circuit chips.
  7. Stambaugh Mark A. (Missouri City TX) Brodhead William H. (Sugarland TX), Packaged semiconductor device with test circuits for determining fabrication parameters.
  8. Swoboda Gary L. (Sugar Land TX), Scan design with expanded access capability.
  9. Carbine Adrian (Portland WA), Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip.
  10. Sato Katsuyuki (Kodaira JPX) Kawamoto Hiroshi (Kodaira JPX) Yanagisawa Kazumasa (Kokubunji JPX), Selective application of voltages for testing storage cells in semiconductor memory arrangements.
  11. Sato Katsuyuki (Kodaira JPX) Kawamoto Hiroshi (Kodaira JPX) Yanagisawa Kazumasa (Kokubunji JPX), Selective application of voltages for testing storage cells in semiconductor memory arrangements.
  12. Kabashima, Katsuhiko; Takemae, Yoshihiro; Nozaki, Shigeki; Ohira, Tsuyoshi; Miyahara, Hatsuo; Kanai, Masakazu; Enomoto, Seiji, Semiconductor integrated circuit device.
  13. Manku Tajinder (Nepean CAX) Song Wenyi (Ottawa CAX), Semiconductor test chip with on wafer switching matrix.
  14. Lee Nai C. (Peekskill NY), System for partitioning and testing submodule circuits of an integrated circuit.
  15. Ovens Kevin M. (Garland TX) Niehaus Jeffrey A. (Dallas TX), Test circuit for screening parts.
  16. Oke Timothy P. (Milpitas CA) Cummings ; II Russell E. (Milpitas CA) Gavrielov Nachum M. (Palo Alto CA), Testable embedded microprocessor and method of testing same.
  17. Blum Arnold (Gechingen DEX) Schettler Helmut (Dettenhausen DEX), Testing an integrated circuit containing a tristate driver and a control signal generating network therefor.

이 특허를 인용한 특허 (67)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Loughmiller, Daniel R.; Sher, Joseph C.; Duesman, Kevin G., Circuit and method for measuring and forcing an internal voltage of an integrated circuit.
  6. Thomas Meany IE; Adrian Sherry IE, Circuit for testing an integrated circuit.
  7. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  8. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  9. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  10. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  11. Koniaris, Kleanthes G.; Burr, James B., Closed loop feedback control of integrated circuits.
  12. Koniaris, Kleanthes G.; Burr, James B., Closed loop feedback control of integrated circuits.
  13. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  14. Masleid,Robert P., Column select multiplexer circuit for a domino random access memory array.
  15. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  16. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  17. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  18. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  19. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  20. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  21. Masleid, Robert P, Dynamic ring oscillators.
  22. Cirkel, Cornelis Oene; Xing, Yizi, Electronic circuit device with a short circuit switch using transistors and method of testing such a device.
  23. Chen, Tien-Min, Feedback-controlled body-bias voltage source.
  24. Koniaris, Kleanthes G.; Burr, James B., Frequency specific closed loop feedback control of integrated circuits.
  25. Koniaris, Kleanthes G.; Burr, James B., Frequency specific closed loop feedback control of integrated circuits.
  26. Koniaris, Kleanthes G.; Burr, James B., Frequency specific closed loop feedback control of integrated circuits.
  27. Koniaris, Kleanthes G.; Burr, James B., Frequency specific closed loop feedback control of integrated circuits.
  28. Uejima, Takanori, High-frequency module.
  29. Banerjee, Sujit; Parthasarathy, Vijay, High-voltage transistor device with integrated resistor.
  30. Banerjee, Sujit; Manley, Martin H., Integrated transistor and anti-fuse programming element for a high-voltage integrated circuit.
  31. Masleid, Robert P, Inverting zipper repeater circuit.
  32. Masleid, Robert P., Inverting zipper repeater circuit.
  33. Masleid, Robert Paul, Inverting zipper repeater circuit.
  34. Masleid, Robert, Leakage efficient anti-glitch filter.
  35. Reddy, Sreenivas Aerra; Arulanandam, Srinivasan; Rajaraman, Venkataraman, Maintaining optimum voltage supply to match performance of an integrated circuit.
  36. Banerjee, Sujit; Pham, Giao Minh, Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit.
  37. Banerjee, Sujit; Pham, Giao Minh, Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit.
  38. Schaffroth, Thilo; Schneider, Ralf, Method and semiconductor component having a device for determining an internal voltage.
  39. Huang, Jensen; Diard, Franck; Saulters, Scott, Method and system for artificially and dynamically limiting the framerate of a graphics processing unit.
  40. Diard, Franck; Kadaba, Ganesh, Methods and system for artifically and dynamically limiting the display resolution of an application.
  41. Li, Sau Yan Keith; Dewey, Thomas Edward; Jamkar, Saket Arun; Parikh, Amit, Power consumption reduction systems and methods.
  42. Masleid, Robert Paul, Power efficient multiplexer.
  43. Masleid, Robert Paul, Power efficient multiplexer.
  44. Masleid, Robert Paul, Power efficient multiplexer.
  45. Masleid, Robert Paul, Power efficient multiplexer.
  46. Frid, Aleksandr; Sriram, Parthasarathy, Power management with dynamic frequency adjustments.
  47. Frid, Aleksandr; Sriram, Parthasarathy, Power management with dynamic frequency adjustments.
  48. Kelleher, Brian M.; Mimberg, Ludger; Kranzusch, Kevin; Lam, John; Velmurugan, Senthil S., Processor performance adjustment system and method.
  49. Alben, Jonah M.; Kranzusch, Kevin, Processor temperature adjustment system and method.
  50. Alben, Jonah M.; Kranzusch, Kevin, Processor voltage adjustment system and method.
  51. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  52. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  53. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  54. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  55. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  56. Poechmueller,Peter, Semiconductor device with test circuit disconnected from power supply connection.
  57. Oh, Sang-Mook; Im, Jae-Hyuk, Semiconductor integrated circuit and method for measuring internal voltage thereof.
  58. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  59. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  60. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  61. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  62. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  63. Suzuki, Shingo; Burr, James, System and method for measuring transistor leakage current with a ring oscillator.
  64. Suzuki,Shingo; Burr,James, System and method for measuring transistor leakage current with a ring oscillator.
  65. Balakrishnan, Balu; LeBlanc, David G. R.; Matthews, David Michael Hugh; Mayell, Robert J., Threshold detection with tap.
  66. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  67. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
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