초록 ▼

In the semiconductor memory device which has nonvolatile memory cells, the bit lines which are typified by high capacitances, are isolated from the input/output nodes of the corresponding sense amplifiers during the amplifying operation of the sense amplifier. A flip-flop circuit, such as a CMOS lat

In the semiconductor memory device which has nonvolatile memory cells, the bit lines which are typified by high capacitances, are isolated from the input/output nodes of the corresponding sense amplifiers during the amplifying operation of the sense amplifier. A flip-flop circuit, such as a CMOS latch circuit, is used for each of the sense amplifiers and a switch circuit is connected between each input/output of each sense amplifier and the data (bit) line associated therewith and is turned OFF immediately before or after commencing of the amplifying operation of the sense amplifier. During the amplifying operation of the sense amplifier, the data (bit) line, having a large parasitic capacitance as a result of being typically connected to a large number of nonvolatile memory cell transistors, such as of the single transistor type having both a floating gate and control gate electrodes, is electrically disconnected (electrically isolated) from the sense amplifier.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor memory device comprising:a first data line;a second data line;a plurality of memory cells each of which has a threshold voltage in accordance with stored data therein and is coupled to one of said first and second data lines;a first precharge circuit coupl

[ What is claimed is:] [1.] A semiconductor memory device comprising:a first data line;a second data line;a plurality of memory cells each of which has a threshold voltage in accordance with stored data therein and is coupled to one of said first and second data lines;a first precharge circuit coupled to said first data line;a second precharge circuit coupled to said second data line;a sense amplifier, coupled to said first data line and to said second data line, having a pair of input terminals one of which is to be fed with a reference first voltage, and amplifying data of a selected memory cell in a read operation;a first switch circuit coupled between said first data line and one of the pair of input terminals of said sense amplifier; anda second switch circuit coupled between said second data line and the other of the pair of input terminals of said sense amplifier,wherein after a write operation is performed, in which data is written in a memory cell in accordance with data set in said sense amplifier, said first and second precharge circuits precharge said first data line and said second data line in said read operation for verifying whether said data is written in said memory cell,wherein said first precharge circuit precharges said first data line to a second voltage, higher than said reference first voltage, when said second precharge circuit precharges said second data line to said reference first voltage, and said second precharge circuit precharges said second data line to said second voltage when said first precharge circuit precharges said first data line to said reference first voltage, andwherein after said first and second precharge circuits precharge said first and second data lines in said read operation, each of said first and second switch circuits is turned ON, and each of said first and second switch circuits is turned OFF during amplification of data associated with said memory cell performed in said write operation by said sense amplifier.