초록 ▼

A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and pr

A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and programs that are run simultaneously on the computer. This is accomplished by dividing the parallel computer into a plurality of processor arrays, each of which can be used independently of the others. This division is made dynamically in the sense that the division can readily be altered and indeed in a time sharing environment may be altered between two successive time slots of the frame. Further, the parallel computer is organized so as to permit the simulation of additional parallel processors by each physical processor in the array and to provide for communication among the simulated parallel processors. This parallel computer also provides for storage of virtual processors in virtual memory. As a result of this design, it is possible to build a parallel computer with a number of physical processors on the order of 1,000,000 and a number of virtual processors on the order of 1,000,000,000,000. Moreover, since the computer can be dynamically reconfigured into a plurality of independent processor arrays, a device this size can be shared by a large number of users with each user operating on only a portion of the entire computer having a capacity appropriate for the problem then being addressed.

대표청구항 ▼

[ What is claimed is:] [1.] A memory subsystem for use in connection with a digital data processing system having a plurality of processing nodes with distributed memory comprising:A. a memory including a plurality of addressable storage locations, each storage location being identified by an addres

[ What is claimed is:] [1.] A memory subsystem for use in connection with a digital data processing system having a plurality of processing nodes with distributed memory comprising:A. a memory including a plurality of addressable storage locations, each storage location being identified by an address having a row address portion and a column address portion;B. a memory controller for performing a memory access operation in connection with said memory and a memory access address, the memory access address having a row portion and a column portion, said memory controller selectively (i) transmitting both the row portion and the column portion to the memory if the row portion differs from a row portion for a previous memory access operation, or (ii) transmitting only the column portion to the memory if the row portion is the same as a row portion for a previous memory access operation.