초록 ▼

A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two

A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilitates the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

대표청구항 ▼

[ What is claimed is:] [1.] A cache memory accessed by an address having an index, said cache memory comprising:a first array of RAM cells containing a first plurality of sequential groups of cells;a second array of RAM cells containing a second plurality of sequential groups of cells and operating

[ What is claimed is:] [1.] A cache memory accessed by an address having an index, said cache memory comprising:a first array of RAM cells containing a first plurality of sequential groups of cells;a second array of RAM cells containing a second plurality of sequential groups of cells and operating at about the same time as said first array, wherein said RAM cells of said first array are interleaved such that a first group of said first plurality of sequential groups corresponds to a first way and each subsequent group of said first plurality of sequential groups corresponds to ways alternating between a second way and said first way, and said RAM cells of said second array are interleaved such that a first group of said second plurality of sequential groups corresponds to said second way and each subsequent group of said second plurality of sequential groups corresponds to ways alternating between said first and second ways;a decoder coupled to said first array and said second array for enabling said first and second arrays at about the same time;a first multiplexer coupled to said first array for selectively outputting contents of said first array; anda second multiplexer coupled to said second array for selectively outputting contents of said second array at about the same time as said first multiplexer.