$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Integrated circuit layout routing using multiprocessing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0760641 (1996-12-04)
발명자 / 주소
  • Jones Edwin
  • Koford James S.
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Mitchell, Silberberg & Knupp LLP
인용정보 피인용 횟수 : 180  인용 특허 : 39

초록

The system propagates wiring and performs memory bookkeeping functions. The system also has the capability to plan an additional route from one target pin toward a first pin. Meetings between routes are designated and resolved. Reservations may be established when a processor plans a route. Mutex lo

대표청구항

[ We claim:] [15.] A method for creating a routing plan for wiring a semiconductor chip surface based on a given netlist, comprising the steps of:establishing a first location, a second location, and a grid system on said chip; andsequentially traversing from said first location to said second locat

이 특허에 인용된 특허 (39)

  1. Rogers Donald L. (San Jose CA), Apparatus and method for tracking and identifying printed circuit assemblies.
  2. Miki Yoshio (Kokubunji JPX) Suzuki Kei (Kokubunji CA JPX) Takamine Yoshio (Albany CA), Apparatus for wire routing of VLSI.
  3. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Bitwise implementation mechanism for a circuit design synthesis procedure.
  4. Kimmel Milton J. (Somers NY), Configurable parallel pipeline image processing system.
  5. Her One-Hsiow A. (6785 Mason Way San Jose CA 95129), Electrical routing through fixed sized module and variable sized channel grids.
  6. Shaefer Craig G. (Charlestown MA), Genetic algorithm.
  7. Guha Aloke (Minneapolis MN) Harp Steven A. (St. Paul MN) Samad Tariq (Minneapolis MN), Genetic algorithm synthesis of neural networks.
  8. Harvey Robert L. (Lexington MA), Genetic algorithm technique for designing neural networks.
  9. Modarres Hossein (Mountain View CA) Raam Susan (Fremont CA) Lai Jiun-Hao (Santa Clara CA), Hierarchical floorplanner.
  10. Pryor Richard L. (Voorhees NJ) Cowhig William M. (Philadelphia PA), Hierarchical, computerized design of integrated circuits.
  11. Hong Se J. (Yorktown Heights NY) Nair Ravindra K. (Peekskill NY) Shapiro Eugene (Stamford CT), High speed machine for the physical design of very large scale integrated circuits.
  12. Chi Mely C. (Murray Hill NJ), Integrated circuits with component placement by rectilinear partitioning.
  13. Linsker Ralph (Scarsdale NY), Iterative method for establishing connections and resulting product.
  14. Kaida Hiromasa (Chiba JPX), Logic cell placement method for semiconductor integrated circuit.
  15. Chene Mon R. (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic placement using positionally asymmetrical partitioning algorithm.
  16. Cocke John (Bedford Village NY) Malm Richard L. (San Jose CA) Shedletsky John J. (North Salem NY), Logic simulation machine.
  17. Hitchcock ; Sr. Robert B. (Binghamton NY) Graf Matthew C. (Highland NY), Logic simulation machine.
  18. Bischoff Gabriel P. (Marlboro MA) Greenberg Steven S. (Bolton MA), Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposi.
  19. Date Hiroshi (Hitachi JPX) Hayashi Terumine (Hitachi JPX), Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placemen.
  20. Aoki Takahiro (Kanagawa JPX), Method for automatically determining wiring routes.
  21. Fournier Serge (Montreal CAX), Method for deriving an interconnection route between elements in an interconnection medium.
  22. Wang Deborah C. (San Jose CA), Method for estimating routability and congestion in a cell placement for integrated circuit chip.
  23. Wong Dale M. (San Francisco CA), Method for partitioning of connected circuit components before placement in one or more integrated circuits.
  24. Wong Dale M. (San Francisco CA), Method for placement of circuit components in an integrated circuit.
  25. Antreich Kurt (Germering DEX) Johannes Frank (Germering DEX) Kleinhans Jurgen (Munich DEX) Sigl Georg (Tutzing DEX), Method for placing modules on a carrier.
  26. Finnerty James L. (Lexington MA), Minimizing the interconnection cost of electronically linked objects.
  27. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  28. Koza John R. (25372 La Rena La. Los Altos Hills CA 94022), Non-linear genetic algorithms for solving problems by finding a fit composition of functions.
  29. Kelly ; Jr. James W. (Redmond WA) Perazzoli ; Jr. Frank L. (Redmond WA) Cutler David N. (Bellevue WA), Object transferring system and method in an object based computer operating system.
  30. Gelatt ; Jr. Charles D. (Chappaqua NY) Kirkpatrick Edward S. (Croton-on-Hudson NY), Optimization of an organization of many discrete elements.
  31. Habra Rafik R. (Wappingers Falls NY) Schanzenbach Erich C. (Dover Plains NY), Parallel approach to chip wiring.
  32. McDermith William O. (Colorado Springs CO) Banki Mehrdad (Colorado Springs CO) Bush Kevin M. (Colorado Springs CO), Partitioning of Boolean logic equations into physical logic devices.
  33. Date Hiroshi (Hitachi) Hayashi Terumine (Hitachi JPX), Placement optimizing method/apparatus and apparatus for designing semiconductor devices.
  34. Smith David C. (Williamstown NJ) Noto Richard (Maple Shade NJ), Routing method in computer aided customization of a two level automated universal array.
  35. Wagner Robert A. (Durham NC) Poirier Charles J. (Red Bank NJ), SIMD machine using cube connected cycles network architecture for vector processing.
  36. Rostoker Michael D. ; Koford James S. ; Jones Edwin R. ; Boyle Douglas B. ; Scepanovic Ranko, Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system.
  37. Putatunda Rathindra N. (Marlton NJ) Smith David C. (Williamstown NJ) McNeary Stephen A. (Somerville NJ), Structured design method for high density standard cell and macrocell layout of VLSI chips.
  38. Toyonaga Masahiko (Osaka JPX) Akino Toshiro (Osaka JPX) Okude Hiroaki (Osaka JPX), System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a red.
  39. Shindo Tatsuya (Kawasaki JPX) Kawamura Kaoru (Yokohama JPX), Wiring-pattern-determination system.

이 특허를 인용한 특허 (180)

  1. Siegel,Andrew; Teig,Steven; Etawil,Hussein, Analytical placement method and apparatus.
  2. Siegel,Andrew; Teig,Steven; Etawil,Hussein, Analytical placement method and apparatus.
  3. Takefumi Hiraga JP, Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor.
  4. Waller, Mark; Parker, Tim; Williams, Mark; Birch, Jeremy; Balsdon, Graham; Sato, Fumiako, Automatic integrated circuit routing using spines.
  5. Waller, Mark; Parker, Tim; Williams, Mark; Birch, Jeremy; Balsdon, Graham; Sato, Fumiako, Automatic integrated circuit routing using spines.
  6. Baldsdon, Graham; Birch, Jeremy; Williams, Mark; Waller, Mark; Parker, Tim; Sato, Fumiaki, Automatic routing system with variable width interconnect.
  7. Baldsdon, Graham; Birch, Jeremy; Williams, Mark; Waller, Mark; Parker, Tim; Sato, Fumiaki, Automatic routing system with variable width interconnect.
  8. Balsdon, Graham; Birch, Jeremy; Williams, Mark; Waller, Mark; Parker, Tim; Sato, Fumiaki, Automatic routing system with variable width interconnect.
  9. Balsdon, Graham; Birch, Jeremy; Williams, Mark; Waller, Mark; Parker, Tim; Sato, Fumiaki, Automatically routing nets according to current density rules.
  10. Balsdon, Graham; Birch, Jeremy; Williams, Mark; Waller, Mark; Parker, Tim; Sato, Fumiaki, Automatically routing nets according to current density rules.
  11. Birch, Jeremy; Waller, Mark; Williams, Mark; Balsdon, Graham; Sato, Fumiaki; Parker, Tim, Automatically routing nets according to parasitic constraint rules.
  12. Birch, Jeremy; Waller, Mark; Williams, Mark; Balsdon, Graham; Sato, Fumiaki; Parker, Tim, Automatically routing nets according to parasitic constraint rules.
  13. Birch, Jeremy; Waller, Mark; Balsdon, Graham, Automatically routing nets with variable spacing.
  14. Birch, Jeremy; Waller, Mark; Balsdon, Graham, Automatically routing nets with variable spacing.
  15. Waller, Mark; Parker, Tim; Williams, Mark; Birch, Jeremy; Balsdon, Graham; Sato, Fumiako, Automation using spine routing.
  16. Hetzel, Asmus, Block interstitching using local preferred direction architectures, tools, and apparatus.
  17. Parrott, Gregory H., Concurrent play on multiple gaming machines.
  18. He, Limin; Yao, So-Zen; Deng, Wenyong; Chen, Jing; Chao, Liang-Jih, Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation.
  19. Teig, Steven; Caldwell, Andrew, Decomposing IC regions and embedding routes.
  20. Waller, Mark; Parker, Tim; Williams, Mark; Birch, Jeremy; Balsdon, Graham; Sato, Fumiako, Design automation using spine routing.
  21. Wiltshire, Michael S.; Lisenbee, James J.; Karmarkar, Jayant S.; Wiltshire, Timothy A., Dual display gaming system and method.
  22. Balsdon, Graham, Filling vacant areas of an integrated circuit design.
  23. Balsdon, Graham, Filling vacant areas of an integrated circuit design.
  24. Gilliland, John J.; Laakso, Jeffrey P.; Kaminkow, Joseph E.; Vasquez, James A., Gaming device having multiple display interfaces.
  25. Gilliland, John G.; Laakso, Jeffrey P.; Kaminkow, Joseph E.; Vasquez, James A., Gaming device having multiple selectable display interfaces based on player's wagers.
  26. Gilliland, John G.; Laakso, Jeffrey P.; Kaminkow, Joseph E.; Vasquez, James A., Gaming device having multiple selectable display interfaces based on player's wagers.
  27. Baerlocher, Anthony J.; Kaminkow, Joseph E.; Vasquez, James A., Gaming device having physical concentric symbol generators which are operable to provide a plurality of different games to a player.
  28. Kaminkow, Joseph E.; Jones, Aaron T., Gaming device having touch activated alternating or changing symbol.
  29. SeLegue, Dylan B.; Wenker, Ross D., Gaming system and method employing multi-directional interaction between multiple concurrently played games.
  30. Marston, Daniel W.; Joung, Sek Hwan, Gaming system and method for providing a triggering event based on a collection of units from different games.
  31. Baerlocher, Anthony J.; Cohen, Alexander Casey Naglestad; Bekarian, Arram; De Waal, Daniel, Gaming system and method for providing an additional gaming currency.
  32. Baerlocher, Anthony J.; Cohen, Alexander Casey Naglestad; Bekarian, Arram; De Waal, Daniel, Gaming system and method for providing an additional gaming currency.
  33. Baerlocher, Anthony J.; Cohen, Alexander Casey Naglestad; Bekarian, Arram; DeWaal, Daniel, Gaming system and method for providing an additional gaming currency.
  34. Baerlocher, Anthony J.; Cohen, Alexander Casey Naglestad; Bekarian, Arram; DeWaal, Daniel, Gaming system and method for providing an additional gaming currency.
  35. Graham, Jacob Thomas; Schlottmann, Gregory A., Gaming system and method for providing different bonus awards based on different types of triggered events.
  36. Graham, Jacob Thomas; Schlottmann, Gregory A., Gaming system and method for providing different bonus awards based on different types of triggered events.
  37. Rowe, Richard E., Gaming system and method for providing play of local first game and remote second game.
  38. Rowe, Richard E., Gaming system and method for providing play of local first game and remote second game.
  39. Muir, David H., Gaming system with linked gaming machines that are configurable to have a same probability of winning a designated award.
  40. Muir, David H., Gaming system with linked gaming machines that are configurable to have a same probability of winning a designated award.
  41. Muir, David H., Gaming system with linked gaming machines that are configurable to have a same probability of winning a designated award.
  42. Teig, Steven; Caldwell, Andrew; Jacques, Etienne, Gridless IC layout and method and apparatus for generating such a layout.
  43. Teig,Steven; Buset,Oscar, Hierarchical routing method and apparatus that use diagonal routes.
  44. Birch, Jeremy, High-speed shape-based router.
  45. Teig, Steven; Caldwell, Andrew, IC layout having topological routes.
  46. Teig, Steven; Caldwell, Andrew; Jacques, Etienne, IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout.
  47. Waller, Mark, Integrated circuit routing and compaction.
  48. Waller, Mark, Integrated circuit routing and compaction.
  49. Waller, Mark, Integrated circuit routing with compaction.
  50. Waller, Mark, Integrated circuit routing with compaction.
  51. Teig, Steven; Overhauser, David; Fujimura, Akira, Integrated circuit wiring architectures to support independent designs.
  52. Teig,Steven; Caldwell,Andrew; Jacques,Etienne, Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's.
  53. He, Limin; Yao, So-Zen; Deng, Wenyong; Chen, Jing; Chao, Liang-Jih, Interconnect routing methods of integrated circuit designs.
  54. Teig, Steven; Buset, Oscar, LP method and apparatus for identifying route propagations.
  55. Teig, Steven; Buset, Oscar, LP method and apparatus for identifying routes.
  56. Teig,Steven; Jacques,Etienne, Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts.
  57. Teig,Steven; Jacques,Etienne, Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts.
  58. Hetzel, Asmus; Malhotra, Anish; Fujimura, Akira; Jacques, Etienne; Frankle, Jon; Harrison, David S.; Feather, Heath; Matveev, Alexandre; King, Roger, Local preferred direction architecture.
  59. Hetzel,Asmus; Malhotra,Anish; Fujimura,Akira; Jacques,Etienne; Frankle,Jon; Harrison,David S.; Feather,Heath; Matveev,Alexandre; King,Roger, Local preferred direction architecture, tools, and apparatus.
  60. Malhotra,Anish; Frankle,Jonathan; Hetzel,Asmus; Jacques,Etienne, Local preferred direction routing.
  61. Wadland, Ken; Lawson, Randall; Radumilo-Franklin, Jelena, Localized routing direction.
  62. Teig, Steven; Buset, Oscar, Method and apparatus for adaptively selecting the wiring model for a design region.
  63. Scheffer, Louis K., Method and apparatus for approximating diagonal lines in placement.
  64. Teig,Steven; Deretsky,Zachary, Method and apparatus for computing capacity of a region for non-Manhattan routing.
  65. Teig,Steven; Caldwell,Andrew, Method and apparatus for computing cost of a path expansion to a surface.
  66. Teig,Steven; Ganley,Joseph L., Method and apparatus for computing placement costs.
  67. Teig, Steven; Ganley, Joseph L., Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies.
  68. Teig,Steven; Ganley,Joseph L., Method and apparatus for considering diagonal wiring in placement.
  69. Teig, Steven; Caldwell, Andrew, Method and apparatus for costing a path expansion.
  70. Teig, Steven; Frankle, Jonathan, Method and apparatus for costing routes of nets.
  71. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a design layout.
  72. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
  73. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
  74. Teig, Steven; Caldwell, Andrew, Method and apparatus for defining vias.
  75. Teig, Steven; Caldwell, Andrew; Jacques, Etienne, Method and apparatus for defining vias.
  76. Teig, Steven; Caldwell, Andrew, Method and apparatus for determining viability of path expansions.
  77. Teig,Steven; Buset,Oscar; Chao,Heng Yi, Method and apparatus for diagonal routing by using several sets of lines.
  78. Malhotra, Anish; Frankle, Jonathan; Hetzel, Asmus, Method and apparatus for generating layout regions with local preferred directions.
  79. Malhotra, Anish; Frankle, Jonathan; Hetzel, Asmus, Method and apparatus for generating layout regions with local preferred directions.
  80. Teig, Steven; Caldwell, Andrew, Method and apparatus for generating multi-layer routes.
  81. Teig, Steven; Ganley, Joseph L., Method and apparatus for generating routes for groups of related node configurations.
  82. Teig, Steven; Caldwell, Andrew, Method and apparatus for generating topological routes for IC layouts using perturbations.
  83. Teig,Steven; Frankle,Jonathan, Method and apparatus for identifying a group of routes for a set of nets.
  84. Teig,Steven; Caldwell,Andrew, Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space.
  85. Teig, Steven; Caldwell, Andrew, Method and apparatus for identifying a path between source and target states.
  86. Teig,Steven; Caldwell,Andrew, Method and apparatus for identifying a path between source and target states.
  87. Teig,Steven; Caldwell,Andrew, Method and apparatus for identifying a path between source and target states in a space with more than two dimensions.
  88. Teig,Steven; Caldwell,Andrew, Method and apparatus for identifying optimized via locations.
  89. Teig, Steven; Buset, Oscar, Method and apparatus for identifying propagation for routes with diagonal edges.
  90. Hetzel,Asmus; Jacques,Etienne; Cherukuri,Deepak, Method and apparatus for local preferred direction routing.
  91. Teig,Steven; Frankle,Jonathan; Jacques,Etienne, Method and apparatus for performing an exponential path search.
  92. Teig, Steven; Jacques, Etienne, Method and apparatus for performing geometric routing.
  93. Teig,Steven; Jacques,Etienne, Method and apparatus for performing routability checking.
  94. Teig,Steven; Ganley,Joseph L., Method and apparatus for placing circuit modules.
  95. Teig,Steven; Ganley,Joseph L., Method and apparatus for pre-computing and using multiple placement cost attributes to quantify the quality of a placement configuration within a partitioned region.
  96. Teig, Steven; Ganley, Joseph L., Method and apparatus for pre-computing and using placement costs within a partitioned region for multiple wiring models.
  97. Teig, Steven; Ganley, Joseph L., Method and apparatus for pre-computing attributes of routes.
  98. Teig, Steven; Ganley, Joseph L., Method and apparatus for pre-computing placement costs.
  99. Teig, Steven; Chao, Heng-Yi, Method and apparatus for pre-computing routes.
  100. Teig,Steven; Ganley,Joseph L.; Chao,Heng Yi, Method and apparatus for pre-computing routes.
  101. Teig, Steven; Caldwell, Andrew, Method and apparatus for producing multi-layer topological routes.
  102. Teig, Steven; Buset, Oscar; Lin, Yang-Trung, Method and apparatus for producing sub-optimal routes for a net by generating fake configurations.
  103. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a function.
  104. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a piecewise linear function to a line.
  105. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a piecewise linear function to a point.
  106. Teig,Steven; Caldwell,Andrew, Method and apparatus for propagating a piecewise linear function to a surface.
  107. Teig,Steven; Caldwell,Andrew, Method and apparatus for propagating cost functions.
  108. Teig, Steven; Caldwell, Andrew, Method and apparatus for proportionate costing of vias.
  109. Teig,Steven; Ganley,Joseph L., Method and apparatus for quantifying the quality of placement configurations in a partitioned region of an integrated circuit layout.
  110. Teig, Steven; Caldwell, Andrew, Method and apparatus for routing.
  111. Teig,Steven; Buset,Oscar, Method and apparatus for routing.
  112. Teig,Steven; Frankle,Jonathan, Method and apparatus for routing.
  113. Teig,Steven; Frankle,Jonathan; Jacques,Etienne; Caldwell,Andrew, Method and apparatus for routing.
  114. Teig,Steven; Frankle,Jonathan; Jacques,Etienne; Caldwell,Andrew, Method and apparatus for routing.
  115. Teig, Steven; Caldwell, Andrew, Method and apparatus for routing a set of nets.
  116. Teig,Steven; Caldwell,Andrew, Method and apparatus for routing a set of nets.
  117. Teig,Steven; Caldwell,Andrew, Method and apparatus for routing groups of paths.
  118. Teig, Steven; Caldwell, Andrew; Jacques, Etienne, Method and apparatus for routing nets in an integrated circuit layout.
  119. Teig, Steven; Caldwell, Andrew, Method and apparatus for routing sets of nets.
  120. Frankle,Jonathan; Caldwell,Andrew, Method and apparatus for routing with independent goals on different layers.
  121. He,Limin; Yao,So Zen; Deng,Wenyong; Chen,Jing; Chao,Liang Jih, Method and apparatus for scalable interconnect solution.
  122. Teig,Steven; Frankle,Jonathan, Method and apparatus for searching for a global path.
  123. Teig,Steven; Frankle,Jonathan, Method and apparatus for searching for a three-dimensional global path.
  124. Teig, Steven; Caldwell, Andrew, Method and apparatus for selecting a route for a net based on the impact on other nets.
  125. Teig,Steven; Frankle,Jonathan, Method and apparatus for solving an optimization problem in an integrated circuit layout.
  126. Teig,Steven; Caldwell,Andrew, Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space.
  127. Teig,Steven; Caldwell,Andrew, Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space.
  128. Teig,Steven; Caldwell,Andrew, Method and apparatus for specifying a distance between an external state and a set of states in space.
  129. Teig,Steven; Ganley,Joseph L., Method and apparatus for storing routes.
  130. Teig,Steven; Ganley,Joseph L., Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement.
  131. Teig, Steven; Caldwell, Andrew, Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring.
  132. Teig, Steven; Caldwell, Andrew, Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs.
  133. Parr, Aaron A.; Rigby, Rodney; Kyrobie, Cody; Ting, Li-Chien, Method and system for bi-directional communication between an integrated circuit (IC) layout editor and various IC pattern data viewers.
  134. Teig,Steven, Method and system for performing placement on non Manhattan semiconductor integrated circuits.
  135. Frankle, Jonathan; Gilchrist, III, John H.; Malhotra, Anish, Method and system for routing.
  136. Franz, Keenan W.; Vaden, Michael T., Method and system for supporting multiple cache configurations.
  137. Sharad Malik ; Lawrence Pileggi ; Eric McCaughrin ; Abhijeet Chakraborty ; Douglas B. Boyle, Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design.
  138. Teig,Steven; Caldwell,Andrew, Method for layout of gridless non manhattan integrated circuits with tile based router.
  139. Wolfgang Brenner DE; Cornelius Cremer DE, Method for management and documentation of contact points of a wiring network.
  140. Waller,Mark; Parker,Tim; Williams,Mark; Birch,Jeremy; Balsdon,Graham; Sato,Fumiaki, Method of automatic shape-based routing of interconnects in spines for integrated circuit design.
  141. Balsdon,Graham; Birch,Jeremy; Williams,Mark; Waller,Mark; Parker,Tim; Sato,Fumiaki, Method of automatically routing nets according to current density rules.
  142. Birch,Jeremy; Waller,Mark; Williams,Mark; Balsdon,Graham; Sato,Fumiaki; Parker,Tim, Method of automatically routing nets according to parasitic constraint rules.
  143. Balsdon,Graham; Birch,Jeremy; Williams,Mark; Waller,Mark; Parker,Tim; Sato,Fumiaki, Method of automatically routing nets using a Steiner tree.
  144. Teig, Steven; Overhauser, David; Fujimura, Akira, Multi-directional wiring on a single metal layer.
  145. Chakanaker, Abhijit; Majhi, Jayanth; Gao, Tong, Multi-threaded track assignment.
  146. Teig,Steven, Non manhattan floor plan architecture for integrated circuits.
  147. Sira G. Sudhindranath ; Anand Sethuraman, Off-grid metal layer utilization.
  148. Sudhindranath Sira G. ; Sethuraman Anand, Off-grid metal layer utilization.
  149. Teig, Steven; Ganley, Joseph L., Partitioning placement method and apparatus.
  150. Teig,Steven; Wang,Maogang, Post processor for optimizing manhattan integrated circuits placements into non manhattan placements.
  151. Teig, Steven; Buset, Oscar, Probabilistic routing method and apparatus.
  152. Teig, Steven; Ganley, Joseph L., Recursive partitioning placement method and apparatus.
  153. He, Limin; Yao, So-Zen; Deng, Wenyong; Chen, Jing; Chao, Liang-Jih, Routing interconnect of integrated circuit designs.
  154. Teig, Steven; Buset, Oscar; Jacques, Etienne, Routing method and apparatus.
  155. Teig,Steven; Buset,Oscar; Jacques,Etienne; Caldwell,Andrew; Frankle,Jonathan, Routing method and apparatus.
  156. Teig,Steven; Buset,Oscar; Jacques,Etienne, Routing method and apparatus that use of diagonal routes.
  157. He, Limin; Yao, So-Zen; Deng, Wenyong; Chen, Jing; Chao, Liang-Jih, Routing methods for integrated circuit designs.
  158. Baerlocher, Anthony J.; Iddings, Cara L.; Schneider, Richard J., Server based gaming system having multiple progressive awards.
  159. Baerlocher, Anthony J.; Iddings, Cara L.; Schneider, Richard J., Server based gaming system having multiple progressive awards.
  160. Breckner, Robert E.; Benbrahim, Jamal; Vasquez, James A.; Bansemer, Mark W.; Baerlocher, Anthony J., Server based gaming system having multiple progressive awards.
  161. Iddings, Cara L.; Dewaal, Daniel; Bullard, Bryan D.; Little, Chad; Manfredi, Vince; Schneider, Richard J., Server based gaming system having multiple progressive awards.
  162. Iddings, Cara L.; Dewaal, Daniel; Bullard, Bryan; Little, Chad; Manfredi, Vince; Schneider, Richard J., Server based gaming system having multiple progressive awards.
  163. Vasquez, James A.; Baerlocher, Anthony J.; Jones, Aaron T.; Bansemer, Mark W., Server based gaming system having multiple progressive awards.
  164. Baerlocher, Anthony J.; Schneider, Richard J.; Iddings, Cara L., Server based gaming system having system triggered loyalty award sequences.
  165. Baerlocher, Anthony J.; Schneider, Richard J.; Iddings, Cara L., Server based gaming system having system triggered loyalty award sequences.
  166. Baerlocher, Anthony J.; Schneider, Richard J.; Iddings, Cara L., Server based gaming system having system triggered loyalty award sequences.
  167. Graham, Jacob; Schlottmann, Greg; Low, Michael N.; Baerlocher, Anthony J.; Schneider, Richard J.; Iddings, Cara L., Server based gaming system having system triggered loyalty award sequences.
  168. Graham, Jacob; Schlottmann, Greg; Low, Michael N.; Baerlocher, Anthony J.; Schneider, Richard J.; Iddings, Cara L., Server based gaming system having system triggered loyalty award sequences.
  169. Iddings, Cara L.; Baerlocher, Anthony J.; Schneider, Richard J., Server based gaming system having system triggered loyalty award sequences.
  170. Iddings, Cara L.; Baerlocher, Anthony J.; Schneider, Richard J., Server based gaming system having system triggered loyalty award sequences.
  171. Iddings, Cara L.; Baerlocher, Anthony J.; Schneider, Richard J., Server based gaming system having system triggered loyalty award sequences.
  172. Iddings, Cara L.; Baerlocher, Anthony J.; Schneider, Richard J., Server based gaming system having system triggered loyalty award sequences.
  173. Iddings, Cara L.; Baerlocher, Anthony J.; Schneider, Richard J., Server based gaming system having system triggered loyalty award sequences.
  174. Teig, Steven; Overhauser, David; Fujimura, Akira, Simulating diagonal wiring directions using Manhattan directional wires.
  175. Teig, Steven; Overhauser, David; Fujimura, Akira, Simulating euclidean wiring directions using manhattan and diagonal directional wires.
  176. Michael S. Wiltshire ; James J. Lisenbee ; Jayant S. Karmarkar ; Timothy A. Wiltshire, Slim terminal gaming system.
  177. Wiltshire, Michael S.; Lisenbee, James J.; Karmarkar, Jayant S.; Wiltshire, Timothy A., Slim terminal gaming system.
  178. Wiltshire,Michael S.; Lisenbee,James J.; Karmarkar,Jayant S.; Wiltshire,Timothy A., Slim terminal gaming system.
  179. Viswanath, Manikandan; Ward, Samuel I., Soft pin insertion during physical design.
  180. Teig,Steven; Caldwell,Andrew, Topological vias route wherein the topological via does not have a coordinate within the region.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로