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Method of forming a self-aligned copper diffusion barrier in vias 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/283
출원번호 US-0858139 (1997-05-19)
발명자 / 주소
  • Geffken Robert M.
  • Luce Stephen E.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Whitham, Curtis & WhithamWalter
인용정보 피인용 횟수 : 181  인용 특허 : 13

초록

A copper diffusion barrier is formed on the side walls of vias connected to copper conductors to prevent copper diffusion into inter-level dielectric. A thin film of copper diffusion barrier material is deposited on the wafer post via etch. A sputter etch is performed to remove barrier material from

대표청구항

[ Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:] [1.] A method of preventing copper poisoning while fabricating an integrated circuit structure, comprising the steps of:etching a via through a dielectric layer to a copper conductor po

이 특허에 인용된 특허 (13)

  1. Klein Richard K. ; Erb Darrell ; Avanzino Steven ; Cheung Robin ; Luning Scott ; Tracy Bryan ; Gupta Subhash ; Lin Ming-Ren, Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device.
  2. Huebner Holger (Baldham DEX), Method for filling via holes in a semiconductor layer structure.
  3. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  4. Carr Jeffrey W. (Fishkill NY) David Lawrence D. (Wappingers Falls NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY) Patrick William J. (Newburgh NY) Rodbell Kenneth P. (Poug, Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor.
  5. Chakravorty Kishore K. (Issaquah WA) Tanielian Minas H. (Bellevue WA), Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers.
  6. Venkatraman Ramnath ; Weitzman Elizabeth J. ; Fiordalice Robert W., Method of forming an interconnect structure.
  7. Inoue Minoru (Kawasaki JPX) Iwama Ryuji (Kuwana JPX), Method of forming electrical contact between interconnection layers located at different layer levels.
  8. Chow Ming-Fea (Poughquagh NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY), Method of forming fine conductive lines, patterns and connectors.
  9. Lou Chine-Gie,TWX, Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits.
  10. Case Christopher J. (New Providence NJ) Cheung Kin P. (Hoboken NJ) Liu Ruichen (Warren NJ) Schutz Ronald J. (Warren NJ) Wagner Richard S. (Bernardsville NJ), Process for fabricating integrated circuits having shallow junctions.
  11. Arleo Paul (Menlo Park CA) Henri Jon (San Jose CA) Hills Graham (Los Gatos CA) Wong Jerry (Fremont CA) Wu Robert (Pleasanton CA), Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting spu.
  12. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  13. Li Jian (Ithaca NY) Mayer James W. (Phoenix AZ) Colgan Evan G. (Suffern NY) Gambino Jeffrey P. (Gaylordsville CT), Self-aligned process for capping copper lines.

이 특허를 인용한 특허 (181)

  1. Thorum, Matthew, Alkaline pretreatment for electroplating.
  2. Klawuhn, Erich R.; Rozbicki, Robert; Dixit, Girish A., Apparatus and methods for deposition and/or etch selectivity.
  3. Klawuhn,Erich R.; Rozbicki,Robert; Dixit,Girish A., Apparatus and methods for deposition and/or etch selectivity.
  4. Mayer, Steven T.; Porter, David W.; Willey, Mark J.; Rash, Robert, Apparatus for wetting pretreatment for enhanced damascene metal filling.
  5. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  6. Pradhan, Anshu A.; Rozbicki, Robert, Atomic layer profiling of diffusion barrier and metal seed layers.
  7. Mayer, Steven T.; Ponnuswamy, Thomas A.; Chua, Lee Peng; Rash, Robert, Automated cleaning of wafer plating assembly.
  8. Mayer, Steven T.; Ponnuswamy, Thomas A.; Chua, Lee Peng; Rash, Robert, Automated cleaning of wafer plating assembly.
  9. Rozbicki,Robert; Danek,Michal, Barrier first method for single damascene trench applications.
  10. Chen, Ling; Marcadal, Christophe, Barrier layer structure for copper metallization and method of forming the structure.
  11. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  12. Reid, Jonathan D.; Mayer, Steven T.; Stowell, R. Marshall; Patton, Evan E.; Hawkins, Jeff A., Clamshell apparatus for electrochemically treating wafers.
  13. Patton,Evan E.; Reid,Jonathan D.; Hawkins,Jeffrey A.; Kalakkad,Dinesh S., Clamshell apparatus with crystal shielding and in-situ rinse-dry.
  14. Patton, Evan E.; Reid, Jonathan D.; Hawkins, Jeffrey A.; Kalakkad, Dinesh S.; Mayer, Steven T., Clamshell apparatus with dynamic uniformity control.
  15. Chua, Lee Peng; Mayer, Steven T.; Ponnuswamy, Thomas A.; Kumar, Santosh, Cleaning electroplating substrate holders using reverse current deplating.
  16. Rash, Robert; Ghongadi, Shantinath; Ganesan, Kousik; He, Zhian; Majid, Tariq; Hawkins, Jeff; Varadarajan, Seshasayee; Buckalew, Bryan, Closed contact electroplating cup assembly.
  17. Huang,Cheng Lin; Hsieh,Ching Hua; Lee,Hsien Ming; Pan,Shing Chyang; Peng,Chao Hsien; Su,Li Lin; Lin,Jing Cheng; Shue,Shao Lin; Liang,Mong Song, Composite barrier layer.
  18. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  19. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  20. He, Zhian; Ramesh, Ashwin; Ghongadi, Shantinath, Control of current density in an electroplating apparatus.
  21. He, Zhian; Ramesh, Ashwin; Ghongadi, Shantinath, Control of current density in an electroplating apparatus.
  22. He, Zhian; Ramesh, Ashwin; Ghongadi, Shantinath, Control of current density in an electroplating apparatus.
  23. Kim, Ki-Bum; Soininen, Pekka J.; Raaijmakers, Ivo, Copper interconnect structure having stuffed diffusion barrier.
  24. Kim, Ki-Bum; Soininen, Pekka J.; Raaijmakers, Ivo, Copper interconnect structure having stuffed diffusion barrier.
  25. Spurlin, Tighe A.; Zhou, Jian; Opocensky, Edward C.; Reid, Jonathan; Mayer, Steven T., Current ramping and current pulsing entry of substrates for electroplating.
  26. Hawkins, Jeffrey Alan; Merrill, Charles Lorenzo; Marchetti, Jason Daniel; Ganesan, Kousik; Buckalew, Bryan L., Deionized water conditioning system and methods.
  27. Wu, Hui-Jung; Juliano, Daniel R.; Wu, Wen; Dixit, Girish, Deposition of doped copper seed layers having improved reliability.
  28. Dulkin, Alexander; Vijayendran, Anil; Yu, Tom; Juliano, Daniel R., Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer.
  29. Hsu,Louis Lu Chen; Mandelman,Jack Allan; Tonti,William Robert; Yang,Chih Chao, Design structures incorporating interconnect structures with liner repair layers.
  30. Mayer, Steven T.; Fu, Haiying; Ponnuswamy, Thomas Anand; Buckalew, Bryan L., Detection of plating on wafer holding apparatus.
  31. Lawrence A. Clevenger ; Louis L. C. Hsu ; Jeremy K. Stephens ; Michael Wise, Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow.
  32. Geffken, Robert M.; Hautala, John J., Dual damascene integration structure and method for forming improved dual damascene integration structure.
  33. Hsin-Tang Peng TW; Fu-Cheng Lin TW; Chun-Wei Chen TW, Dual damascene process which prevents diffusion of metals and improves trench-to-via alignment.
  34. Bin Zhao ; Liming Tsau, Dual-damascene interconnect structures and methods of fabricating same.
  35. Yang, Chih-Chao; Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom, Electrical fuse structure and method of fabricating same.
  36. Stowell, R. Marshall; Feng, Jingbin; Porter, David W., Electrofill vacuum plating cell.
  37. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  38. Feng, Jingbin; He, Zhian; Rash, Robert; Mayer, Steven T., Electroplating apparatus with vented electrolyte manifold.
  39. Rash, Robert; Ghongadi, Shantinath; Ganesan, Kousik; He, Zhian; Majid, Tariq; Hawkins, Jeff; Varadarajan, Seshasayee; Buckalew, Bryan, Electroplating cup assembly.
  40. Kitch, Vassili, Fabrication of copper-containing region such as electrical interconnect.
  41. Kitch,Vassili, Fabrication technique using sputter etch and vacuum transfer.
  42. Hautala,John J., GCIB processing of integrated circuit interconnect structures.
  43. Skinner, Wesley J.; Hautala, John J., GCIB processing to improve interconnection vias and improved interconnection via.
  44. Zhou, Jian; Sweeney, Cian; He, Zhian; Reid, Jonathan David, Geometry and process optimization for ultra-high RPM plating.
  45. Farrar,Paul A., Hplasma treatment.
  46. Liu Chung-Shi,TWX ; Shue Shau-Lin,TWX ; Yu Chen-Hua,TWX, In-situ cleaning process for Cu metallization.
  47. Farrar, Paul A., Integrated circuit and seed layers.
  48. Farrar,Paul A., Integrated circuit and seed layers.
  49. Praburam Gopalraja ; Jianming Fu ; Fusen Chen ; Girish Dixit ; Zheng Xu ; Sankaram Athreya ; Wei D. Wang ; Ashok K. Sinha, Integrated copper fill process.
  50. Berke, Aaron; Rash, Robert; Mayer, Steven T.; Kumar, Santosh; Chua, Lee Peng, Integrated elastomeric lipseal and cup bottom for reducing wafer sticking.
  51. Gopalraja Praburam ; Fu Jianming ; Chen Fusen ; Dixit Girish ; Xu Zheng ; Athreya Sankaram ; Wang Wei D. ; Sinha Ashok K., Integrated process for copper via filling.
  52. Chung,Hua; Maity,Nirmalya; Yu,Jick; Mosely,Roderick Craig; Chang,Mei, Integration of ALD tantalum nitride for copper metallization.
  53. Yang, Chih-Chao; Murray, Conal E., Interconnect structure and method for Cu/ultra low k integration.
  54. Yang, Chih-Chao; Murray, Conal E., Interconnect structure and method for Cu/ultra low k integration.
  55. Yang, Chih-Chao; Hsu, Louis C.; Joshi, Rajiv V., Interconnect structure and method for forming the same.
  56. Yang, Chih-Chao; Spooner, Terry A.; van der Straten, Oscar, Interconnect structure containing non-damaged dielectric and a via gouging feature.
  57. Peng, Chao-Hsien; Huang, Hsin-Yen; Lee, Hsiang-Huan; Shue, Shau-Lin, Interconnect structures comprising flexible buffer layers.
  58. Peng, Chao-Hsien; Huang, Hsin-Yen; Lee, Hsiang-Huan; Shue, Shau-Lin, Interconnect structures comprising flexible buffer layers.
  59. Hsu,Louis Lu Chen; Mandelman,Jack Allan; Tonti,William Robert; Yang,Chih Chao, Interconnect structures with linear repair layers and methods for forming such interconnection structures.
  60. Tsu,Robert; McPherson,Joe W.; McKee,William R.; Bonifield,Thomas, Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer.
  61. Feng, Jingbin; Stowell, Marshall; Wilmot, Frederick D., Lipseals and contact elements for semiconductor electroplating apparatuses.
  62. Feng, Jingbin; Stowell, Robert Marshall; Ghongadi, Shantinath; Ramesh, Ashwin, Lipseals and contact elements for semiconductor electroplating apparatuses.
  63. Barnak,John P.; Chau,Robert S.; Liang,Chunlin, MOSFET gate electrodes having performance tuned work functions and methods of making same.
  64. Ueno, Kazuyoshi, Manufacturing method of a semiconductor device.
  65. Kim, Seung Hyun, Metal line of semiconductor device and method of manufacturing the same.
  66. Akram,Salman, Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same.
  67. Hashim, Imran; Chiang, Tony; Chin, Barry, Method and apparatus for forming improved metal interconnects.
  68. Hashim, Imran; Chiang, Tony; Chin, Barry, Method and apparatus for forming improved metal interconnects.
  69. Hashim,Imran; Chiang,Tony; Chin,Barry, Method and apparatus for forming improved metal interconnects.
  70. Pradhan, Anshu A.; Hayden, Douglas B.; Kinder, Ronald L.; Dulkin, Alexander, Method and apparatus for increasing local plasma density in magnetically confined plasma.
  71. Danek, Michal; Rozbicki, Robert, Method for depositing a diffusion barrier for copper interconnect applications.
  72. Rozbicki, Robert; Danek, Michal, Method for depositing a diffusion barrier for copper interconnect applications.
  73. Chiang, Tony; Yao, Gongda; Ding, Peijun; Chen, Fusen E.; Chin, Barry L.; Kohara, Gene Y.; Xu, Zheng; Zhang, Hong, Method for depositing a diffusion barrier layer and a metal conductive layer.
  74. Malhotra, Sandra G.; Simon, Andrew Herbert, Method for depositing a metal layer on a semiconductor interconnect structure.
  75. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  76. Chen, Chien-Hui; Yang, Ming-Kun; Liu, Tsang-Yu; Ho, Yen-Shih, Method for forming chip package.
  77. Huang, Cheng-Lin; Hsieh, Ching-Hua; Lee, Hsien-Ming; Pan, Shing-Chyang; Peng, Chao-Hsien; Su, Li-Lin; Lin, Jing-Cheng; Shue, Shao-Lin; Liang, Mong-Song, Method for forming composite barrier layer.
  78. Marathe, Amit P.; Wang, Pin-Chin Connie; Woo, Christy Mei-Chu, Method for forming conductor reservoir volume for integrated circuit interconnects.
  79. Jin Gyo-Young,KRX, Method for forming contact.
  80. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  81. Wege, Stephan; Moll, Peter, Method for manufacturing a conductor structure for an integrated circuit.
  82. Chooi Simon,SGX ; Xu Yi,SGX ; Aliyu Yakub ; Zhou Mei-Sheng,SGX ; Sudijono John Leonard,SGX ; Gupta Subhash,SGX ; Roy Sudipto Ranendra,SGX ; Ho Paul,SGX, Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent.
  83. Rozbicki, Robert T.; Danek, Michal; Klawuhn, Erich R., Method of depositing a diffusion barrier for copper interconnect applications.
  84. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  85. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  86. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  87. Chiang, Tony; Yao, Gongda; Ding, Peijun; Chen, Fusen E.; Chin, Barry L.; Kohara, Gene Y.; Xu, Zheng; Zhang, Hong, Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate.
  88. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing copper seed on semiconductor substrates.
  89. Ye,Yan; Zhao,Xiaoye; Du,Hong, Method of fabricating a dual damascene interconnect structure.
  90. Ye,Yan; Zhao,Xiaoye; Du,Hong, Method of fabricating a dual damascene interconnect structure.
  91. Lan Shih-Ming,TWX, Method of fabricating a dual damascene structure.
  92. Liu,Chi Wen; Wang,Ying Lang, Method of forming a protective layer over Cu filled semiconductor features.
  93. Woo, Christy Mei-Chu; Pangrle, Suzette K.; Ngo, Minh Van, Method of forming low resistance barrier on low k interconnect.
  94. Woo, Christy Mei-Chu; Pangrle, Suzette K.; Wang, Connie Pin-Chin, Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer.
  95. Ito Nobukazu,JPX ; Matsubara Yoshihisa,JPX, Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface.
  96. Lin, Jing-Cheng, Method of forming multilayer diffusion barrier for copper interconnections.
  97. Lin, Jing-Cheng, Method of forming multilayer diffusion barrier for copper interconnections.
  98. Liu, Nai-Wei; Wu, Zhen-Cheng; Huang, Cheng-Lin; Huang, Po-Hsiang; Wang, Yung-Chih; Su, Shu-Hui; Chen, Dian-Hau; Mii, Yuh-Jier, Method of making a semiconductor device including barrier layers for copper interconnect.
  99. Hidemitsu Aoki JP, Method of manufacturing a semiconductor device.
  100. Huang Yimin,TWX ; Yew Tri-Rung,TWX ; Lur Water,TWX, Method of manufacturing copper interconnect.
  101. Ling Chen ; Seshadri Ganguli ; Wei Cao ; Christophe Marcadal, Method of using a barrier sputter reactor to remove an underlying barrier layer.
  102. Karthikeyan,Subramanian; Merchant,Sailesh M., Method to avoid copper contamination of a via or dual damascene structure.
  103. Mei-Sheng Zhou SG; Simon Chooi SG; Yi Xu SG, Method to form damascene interconnects with sidewall passivation to protect organic dielectrics.
  104. Chu, Karen; Vijayendran, Anil; Danek, Michal, Method to improve barrier layer adhesion.
  105. Reid, Jonathan D.; Mayer, Steven T.; Varadarajan, Seshasayee; Smith, David C.; Patton, Evan E.; Kalakkad, Dinesh S.; Lind, Gary, Methods and apparatus for controlled-angle wafer immersion.
  106. Reid, Jonathan D.; Mayer, Steven T.; Varadarajan, Seshasayee; Smith, David C.; Patton, Evan E.; Kalakkad, Dinesh S.; Lind, Gary; Hill, Richard S., Methods and apparatus for controlled-angle wafer positioning.
  107. Reid,Jonathan D.; Mayer,Steven T.; Varadarajan,Seshasayee; Smith,David C.; Patton,Evan E.; Kalakkad,Dinesh S.; Lind,Gary; Hill,Richard S., Methods and apparatus for controlled-angle wafer positioning.
  108. Mayer, Steven T.; Stowell, R. Marshall; Patton, Evan E.; Varadarajan, Seshasayee, Methods and apparatus for controlling electrolyte flow for uniform plating.
  109. Dulkin, Alexander; Rairkar, Asit; Greer, Frank; Pradhan, Anshu A.; Rozbicki, Robert, Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer.
  110. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  111. Rozbicki, Robert, Methods and apparatus for resputtering process that improves barrier coverage.
  112. Buckalew, Bryan L.; Mayer, Steven T.; Ponnuswamy, Thomas A.; Rash, Robert; Blackman, Brian Paul; Higley, Doug, Methods and apparatus for wetting pretreatment for through resist metal plating.
  113. Buckalew, Bryan L.; Mayer, Steven T.; Ponnuswamy, Thomas A.; Rash, Robert; Blackman, Brian; Higley, Doug, Methods and apparatus for wetting pretreatment for through resist metal plating.
  114. Chua, Lee Peng; Buckalew, Bryan L.; Ponnuswamy, Thomas Anand; Blackman, Brian Paul; Hosack, Chad Michael; Mayer, Steven T., Methods and apparatus for wetting pretreatment for through resist metal plating.
  115. Chua, Lee Peng; Buckalew, Bryan L.; Ponnuswamy, Thomas Anand; Blackman, Brian; Hosack, Chad Michael; Mayer, Steven T., Methods and apparatus for wetting pretreatment for through resist metal plating.
  116. Kumar, Santosh; Buckalew, Bryan L.; Mayer, Steven T.; Ponnuswamy, Thomas; Hosack, Chad Michael; Rash, Robert; Chua, Lee Peng; Porter, David, Methods and apparatuses for cleaning electroplating substrate holders.
  117. Jiang,Ping; Kraft,Rob; Xing,Guoqiang; Kirmse,Karen H. R.; Zielinski,Eden, Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities.
  118. Akram, Salman, Methods for making metallization structures for semiconductor device interconnects.
  119. Akram, Salman, Methods for making metallization structures for semiconductor device interconnects.
  120. Ostrowski, John Floyd; Rash, Robert, Multi-contact lipseals and associated electroplating methods.
  121. Chen, Ling; Ganguli, Seshadri; Cao, Wei; Marcadal, Christophe, Multi-step barrier deposition method.
  122. Gopalraja,Praburam; Fu,Jianming; Chen,Fusen; Dixit,Girish; Xu,Zheng; Wang,Wei; Sinha,Ashok K., Multi-step magnetron sputtering process.
  123. Lin,Jing Cheng, Multilayer diffusion barrier for copper interconnections.
  124. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Thomas; Wu, Wen, Multistep method of depositing metal seed layers.
  125. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Tom; Wu, Wen, Multistep method of depositing metal seed layers.
  126. Wojtczuk, Steven J.; Moe, James G.; Little, Roger G., Nanophotovoltaic devices.
  127. Gopalraja, Praburam; Fu, Jianming; Chen, Fusen; Dixit, Girish; Xu, Zheng; Wang, Wei; Sinha, Ashok K., Operating a magnetron sputter reactor in two modes.
  128. He, Zhian; Feng, Jingbin; Ghongadi, Shantinath; Wilmot, Frederick D., Plating cup with contoured cup bottom.
  129. He, Zhian; Feng, Jingbin; Ghongadi, Shantinath; Wilmot, Frederick D., Plating cup with contoured cup bottom.
  130. Lin,Zong Huei; Yu,Art; Hsu,Chia Rung; Tsai,Teng Chun, Polish method for semiconductor device planarization.
  131. Thorum, Matthew S.; Mayer, Steven T., Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias.
  132. Chen, Ling; Ganguli, Seshadri; Cao, Wei; Marcadal, Christophe, Process for removing an underlying layer and depositing a barrier layer in one reactor.
  133. Mei Sheng Zhou SG; John Sudijono SG; Subhash Gupta SG; Sudipto Roy SG; Paul Ho SG; Xu Yi SG; Simon Chooi SG; Yakub Aliyu SG, Process without post-etch cleaning-converting polymer and by-products into an inert layer.
  134. Ghongadi, Shantinath; Rash, Robert; Hawkins, Jeff; Varadarajan, Seshasayee; Majid, Tariq; Ganesan, Kousik; Buckalew, Bryan; Evans, Brian, Rapidly cleanable electroplating cup seal.
  135. Xi,Ming; Smith,Paul Frederick; Chen,Ling; Yang,Michael X.; Chang,Mei; Chen,Fusen; Marcadal,Christophe; Lin,Jenny C., Reliability barrier integration for Cu application.
  136. Lu, Jiong-Ping; Lin, Ching-Te, Reliable interconnects with low via/contact resistance.
  137. Yang, Chih-Chao; Van Der Straten, Oscar, Reliable via contact interconnect structure.
  138. Kailasam, Sridhar; Rozbicki, Robert; Yu, Chentao; Hayden, Douglas, Resputtering process for eliminating dielectric damage.
  139. Juliano, Daniel R., Selective resputtering of metal seed layers.
  140. Gopalraja, Praburam; Fu, Jianming; Tang, Xianmin; Forster, John C.; Kelkar, Umesh, Self-ionized and capacitively-coupled plasma for sputtering and resputtering.
  141. Gopalraja,Praburam; Fu,Jianming; Tang,Xianmin; Forster,John C.; Kelkar,Umesh, Self-ionized and capacitively-coupled plasma for sputtering and resputtering.
  142. Ding, Peijun; Tao, Rong; Xu, Zheng; Lubben, Daniel C.; Rengarajan, Suraj; Miller, Michael A.; Sundarrajan, Arvind; Tang, Xianmin; Forster, John C.; Fu, Jianming; Mosely, Roderick C.; Chen, Fusen; Gopalraja, Praburam, Self-ionized and inductively-coupled plasma for sputtering and resputtering.
  143. Ding, Peijun; Tao, Rong; Xu, Zheng; Lubben, Daniel C.; Rengarajan, Suraj; Miller, Michael A.; Sundarrajan, Arvind; Tang, Xianmin; Forster, John C.; Fu, Jianming; Mosely, Roderick C.; Chen, Fusen; Gopalraja, Praburam, Self-ionized and inductively-coupled plasma for sputtering and resputtering.
  144. Ding, Peijun; Tao, Rong; Xu, Zheng; Lubben, Daniel C.; Rengarajan, Suraj; Miller, Michael A.; Sundarrajan, Arvind; Tang, Xianmin; Forster, John C.; Fu, Jianming; Mosely, Roderick C.; Chen, Fusen; Gopalraja, Praburam, Self-ionized and inductively-coupled plasma for sputtering and resputtering.
  145. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor contact barrier.
  146. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor contact barrier.
  147. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor contact barrier.
  148. Ito, Nobukazu; Matsubara, Yoshihisa, Semiconductor device and manufacturing method thereof.
  149. Motoyama, Koichi, Semiconductor device and method for manufacturing the same.
  150. Clevenger, Lawrence A.; Hsu, Louis L. C.; Stephens, Jeremy K.; Wise, Michael, Semiconductor device with diamond-like carbon layer as a polish-stop layer.
  151. Nguyen, Son Van; Xia, Li-Qun; Nemani, Srinivas D., Side wall passivation films for damascene cu/low k electronic devices.
  152. You,Lu; Wang,Fei; Ngo,Minh Van, Single damascene integration scheme for preventing copper contamination of dielectric layer.
  153. Bass William Scott, Spacer - defined dual damascene process method.
  154. Jianming Fu ; Praburam Gopalraja, Sputtering method utilizing an extended plasma region.
  155. Praburam Gopalraja ; Jianming Fu, Sputtering target having an annular vault.
  156. Yu, Young Sub; Kim, Seok Sik; Hwang, Ki Hyun; Lim, Han Jin; Choi, Sung Je, Storage electrode of a semiconductor memory device and method for fabricating the same.
  157. Chen, Chung-Hsien; Ko, Ting-Chu; Chang, Chih-Hao; Chang, Chih-Sheng; Chang, Shou-Zen; Wann, Clement Hsingjen, Strained structure of a semiconductor device.
  158. Yang, Chih Chao; Spooner, Terry A.; van der Straten, Oscar, Structure and method for metal integration.
  159. Mehta, Sanjay C.; Edelstein, Daniel C.; Fitzsimmons, John A.; Grunow, Stephan; Nye, III, Henry A.; Rath, David L., Structure and method of chemically formed anchored metallic vias.
  160. Farrar, Paul A., Structures and methods to enhance copper metallization.
  161. Farrar, Paul A., Structures and methods to enhance copper metallization.
  162. Farrar,Paul A., Structures and methods to enhance copper metallization.
  163. Farrar,Paul A., Structures and methods to enhance copper metallization.
  164. Chen, Ling; Ganguli, Seshadri; Cao, Wei; Marcadal, Christophe, Tantalum barrier layer for copper metallization.
  165. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  166. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  167. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  168. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  169. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  170. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  171. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  172. You, Lu; Wang, Fei; Hopper, Dawn M., Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers.
  173. You, Lu; Hopper, Dawn M.; Pangrle, Suzette K., Use of sic for preventing copper contamination of low-k dielectric layers.
  174. You, Lu; Hopper, Dawn M.; Ngo, Minh Van, Use of sion for preventing copper contamination of dielectric layer.
  175. Kinder, Ronald L.; Pradhan, Anshu A., Use of ultra-high magnetic fields in resputter and plasma etching.
  176. Praburam Gopalraja ; Jianming Fu ; Fusen Chen ; Girish Dixit ; Zheng Xu ; Wei Wang ; Ashok K. Sinha, Vault shaped target and magnetron operable in two sputtering modes.
  177. Praburam Gopalraja ; Jianming Fu ; Wei Wang, Vault-shaped target and magnetron having both distributed and localized magnets.
  178. Prabhakar, Vinay; Buckalew, Bryan L.; Ganesan, Kousik; Ghongadi, Shantinath; He, Zhian; Mayer, Steven T.; Rash, Robert; Reid, Jonathan D.; Takada, Yuichi; Zibrida, James R., Wafer electroplating apparatus for reducing edge defects.
  179. Mayer, Steven T.; Porter, David W.; Willey, Mark J., Wetting pretreatment for enhanced damascene metal filling.
  180. Ranjan, Manish; Ghongadi, Shantinath; Wilmot, Frederick Dean; Hill, Douglas; Buckalew, Bryan L., Wetting wave front control for reduced air entrapment during wafer entry into electroplating bath.
  181. Ranjan, Manish; Ghongadi, Shantinath; Wilmot, Frederick Dean; Hill, Douglas; Buckalew, Bryan L., Wetting wave front control for reduced air entrapment during wafer entry into electroplating bath.
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