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Multi-chip land grid array carrier 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/18
출원번호 US-0993793 (1997-12-19)
발명자 / 주소
  • Samaras William A.
  • Phillips Paul T.
  • Brownell Michael P.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 53  인용 특허 : 4

초록 ▼

A land grid array (LGA) carrier includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conduct

대표청구항 ▼

[ What is claimed is:] [1.] A land grid array (LGA) carrier, comprising:an interposer having a first surface and a second surface opposite the first surface;a plurality of locations on the first surface adapted to receive a plurality of semiconductor dies and passive components, wherein the passive

이 특허에 인용된 특허 (4)

  1. Gaudenzi Gene J. (Purdy\s NY) Nihal Perwaiz (Hopewell Junction NY), Direct chip attach module (DCAM).
    상세보기
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  3. Behlen James F. (Sunnyvale CA) Hussain Rafiqul (Fremont CA) Haq Munir (San Jose CA), Micro BGA stacking scheme.
    상세보기
  4. Mok Sammy L. (Cupertino CA), Mounting assembly for multiple chip module with more than one substrate and computer using same.
    상세보기

이 특허를 인용한 특허 (53)

  1. Prakash, Mani; Holden, Thomas T.; Smalley, Jeffory L.; Viswanath, Ram S.; Coury, Bassam N.; Ziakas, Dimitrios; Zhao, Chong J.; Thibado, Jonathan W.; Murtagian, Gregorio R.; Liu, Kuang C.; Swaminathan, Rajasekaran; Zhang, Zhichao; Lynch, John M.; Llapitan, David J.; Ganesan, Sanka; Li, Xiang; Vergis, George, CPU package substrates with removable memory mechanical interfaces.
    상세보기
  2. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.
    상세보기
  3. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Compact system module with built-in thermoelectric cooling.
    상세보기
  4. Ahn,Kie Y.; Forbes,Leonard; Cloud,Eugene H., Compact system module with built-in thermoelectric cooling.
    상세보기
  5. Ramalingam,Suresh; Murali,Venkatesan; Cook,Duane, Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials.
    상세보기
  6. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.
    상세보기
  7. Chakravorty,Kishore K.; Wermer,Paul H.; Figueroa,David G.; Gupta,Debabrata, Data processing system comprising ceramic/organic hybrid substrate with embedded capacitors.
    상세보기
  8. Lee,Teck Kheng; Lee,Kian Chai; Khoo,Sian Yong, Double bumping of flexible substrate for first and second level interconnects.
    상세보기
  9. Chakravorty, Kishore K., Electronic assemblies and systems comprising interposer with embedded capacitors.
    상세보기
  10. Chakravorty,Kishore K., Electronic assemblies and systems comprising interposer with embedded capacitors.
    상세보기
  11. Chakravorty, Kishore K.; Wermer, Paul H.; Figueroa, David G.; Gupta, Debabrata, Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors.
    상세보기
  12. Chakravorty, Kishore K.; Wermer, Paul H.; Figueroa, David G.; Gupta, Debabrata, Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture.
    상세보기
  13. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  14. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  15. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  16. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  17. Moon,Ow Chee; Koon,Eng Meow, Flexible ball grid array chip scale packages.
    상세보기
  18. Lee, Teck Kheng, Flip chip packaging using recessed interposer terminals.
    상세보기
  19. Lee,Teck Kheng, Flip chip packaging using recessed interposer terminals.
    상세보기
  20. Akram, Salman, High density stackable and flexible substrate-based devices and systems and methods of fabricating.
    상세보기
  21. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.
    상세보기
  22. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
    상세보기
  23. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
    상세보기
  24. Lee,Teck Kheng, Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods.
    상세보기
  25. Lee,Teck Kheng, Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice.
    상세보기
  26. Caletka, David Vincent; Darbha, Krishna; Infantolino, William; Johnson, Eric Arthur, Land grid array stiffener for use with flexible chip carriers.
    상세보기
  27. Caletka, David Vincent; Darbha, Krishna NMN; Infantolino, William NMN; Johnson, Eric Arthur, Land grid array stiffener use with flexible chip carriers.
    상세보기
  28. Lee, Teck Kheng, Method and apparatus for dielectric filling of flip chip on interposer assembly.
    상세보기
  29. Andric, Anthony M.; Hill, Ruel; Markwardt, Doug, Method and apparatus for direct connection between two integrated circuits via a connector.
    상세보기
  30. Buley, Todd H.; Lam, Roger; O'Connor, Daniel; Perry, Charles Hampton, Method of assembling a land grid array module.
    상세보기
  31. Lee, Teck Kheng, Method of manufacturing microelectronic devices, including methods of underfilling microelectronic components through an underfill aperture.
    상세보기
  32. Lee, Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  33. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  34. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  35. Yean, Tay Wuu; Ai-Chie, Wang, Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages.
    상세보기
  36. Lee, Teck Kheng; Tan, Cher Khng Victor, Methods of forming semiconductor assemblies.
    상세보기
  37. Shang, Alain; Dair, Edwin, Methods, apparatus, and systems of fiber optic modules, elastomeric connections, and retention mechanisms therefor.
    상세보기
  38. Lee,Teck Kheng, Microelectronic devices including underfill apertures.
    상세보기
  39. Jeffrey W. Day ; Steven L. Pollock, PLGA-BGA socket using elastomer connectors.
    상세보기
  40. George F. Raiser ; Bob Sundahl ; Ravi Mahajan, Partial underfill for flip-chip electronic packages.
    상세보기
  41. Raiser, George F.; Sundahl, Bob; Mahajan, Ravi, Partial underfill for flip-chip electronic packages.
    상세보기
  42. Cook Duane ; Murali Venkatesan ; Ramalingam Suresh ; Vodrahalli Nagesh, Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state.
    상세보기
  43. Cook, Duane; Ramalingam, Suresh, Process line for underfilling a controlled collapse.
    상세보기
  44. Lee, Teck Kheng, Semiconductor device assemblies.
    상세보기
  45. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures.
    상세보기
  46. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures and methods for assembling the same.
    상세보기
  47. Fritz, Donald S., Semiconductor package with stress inhibiting intermediate mounting substrate.
    상세보기
  48. Fan, Zhineng; Le, Ai D.; Li, Che-Yu, Shielded carrier with components for land grid array connectors.
    상세보기
  49. Ahn, Kie Y.; Forbes, Leonard, Silicon interposer with optical connections.
    상세보기
  50. Moden, Walter L.; Corisis, David J.; Mess, Leonard E.; Kinsman, Larry D., Stackable ceramic FBGA for high thermal applications.
    상세보기
  51. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.
    상세보기
  52. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
    상세보기
  53. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
    상세보기

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