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Low contact resistance and low junction leakage metal interconnect contact structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/43
출원번호 US-0213021 (1998-12-16)
발명자 / 주소
  • Blair Christopher S.
  • Saadat Irfan A.
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Limbach & Limbach L.L.P.
인용정보 피인용 횟수 : 53  인용 특허 : 7

초록

A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which ex

대표청구항

[ What is claimed is:] [6.] A low contact resistance and low junction leakage metal interconnect contact structure for use in integrated circuits that include a semiconductor substrate, the metal interconnect contact structure comprising:an interconnect dielectric material layer disposed on the surf

이 특허에 인용된 특허 (7)

  1. Wang Qingfeng ; Maex Karen Irma Josef,BEX, CoSi.sub.2 salicide method.
  2. Cherniawski Michael (Austin TX) Barker Jeffrey M. (Manor TX) Pyle Ronald E. (Austin TX) Kaushik Vidya S. (Austin TX), Method for contacting a semiconductor device.
  3. Bornstein Johnathan G. (Cupertino CA) Caldwell Roger (Milpitas CA), Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an asso.
  4. Ajika Natsuo (Hyogo JPX) Arima Hideaki (Hyogo JPX), Multi-layered interconnection structure for a semiconductor device.
  5. Wei Chin-Shih (Fremont CA) Fraser David B. (Danville CA) Murali Venkatesan (San Jose CA), Process for formation of a self aligned titanium nitride/cobalt silicide bilayer.
  6. Dass M. Lawrence A. (Fremont CA) Cheng Peng (Campbell CA) Fraser David B. (Danville CA), Process for formation of epitaxial cobalt silicide and shallow junction of silicon.
  7. Ohsaki Akihiko (Hyogo JPX) Yamaguchi Sumio (Hyogo JPX) Ishii Atsushi (Hyogo JPX) Maekawa Kazuyoshi (Hyogo JPX) Fujisawa Masahiko (Hyogo JPX), Semiconductor device comprising composite barrier layer.

이 특허를 인용한 특허 (53)

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  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
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  4. Ide, Kenichi, Contact plug penetrating a metallic transistor.
  5. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
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  7. Pan, James N.; Besser, Paul R.; Woo, Christy; Ngo, Minh Van; Yin, Jinsong, Engineered metal gate electrode.
  8. Pan,James N.; Besser,Paul R.; Woo,Christy; Ngo,Minh Van; Yin,Jinsong, Engineered metal gate electrode.
  9. Huang, Chien-Chung; Ho, Nien-Ting, Fabricating method of semiconductor elements.
  10. Nemouchi, Fabrice; Bourjot, Emilie, Fabrication method of a transistor with improved field effect.
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  15. Chiang, Wen-Tai; Lin, Chun-Hsien, Manufacturing method of metal oxide semiconductor transistor.
  16. Chumakov, Dmytro, Mask-based silicidation for FEOL defectivity reduction and yield boost.
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  27. Ueno Kazuyoshi,JPX, Method for manufacturing a semiconductor device.
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  31. Tsao, Po-Chao; Lin, Chien-Ting, Method of forming metal silicide layer.
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  38. Hung, Ching-Wen; Huang, Chih-Sen; Wu, Yi-Ching, Multi-metal gate semiconductor device having triple diameter metal opening.
  39. Paton, Eric N.; Wang, Haihong; Xiang, Qi, Offset spacer process for forming N-type transistors.
  40. Park,Jae hyun; An,Hyeong geun; Ahn,Su jin; Song,Yoon jong; Youn,Hyung joo; Kim,Kyu chul, PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same.
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  46. Sohn, Dong Kyun; Park, Ji Soo; Bae, Jong Uk, Semiconductor device including ternary phase diffusion barrier.
  47. Liao, Duan Quan; Chen, Yikun; Tey, Ching-Hwa; Zhu, Xiao Zhong, Semiconductor structure and process thereof.
  48. Hung, Ching-Wen; Huang, Chih-Sen; Tsao, Po-Chao, Semiconductor structure having contact plug and metal gate transistor and method of making the same.
  49. Hung, Ching-Wen; Huang, Chih-Sen; Tsao, Po-Chao; Chen, Chieh-Te, Semiconductor structure having contact plug and method of making the same.
  50. Hung, Ching-Wen; Huang, Chih-Sen; Tsao, Po-Chao; Chen, Chieh-Te, Semiconductor structure having contact plug and method of making the same.
  51. Wu, Yi-Ching; Huang, Chih-Sen; Hung, Ching-Wen, Semiconductor structure having metal gate and manufacturing method thereof.
  52. Hung, Ching-Wen; Huang, Chih-Sen, Semiconductor structure with hard mask disposed on the gate structure.
  53. Bao, Tien I; Jang, Syun-Ming, Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration.
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