$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] High speed memory self-timing circuitry and methods for implementing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-008/00
출원번호 US-0956981 (1997-10-24)
발명자 / 주소
  • Kornachuk Steve P.
  • Becker Scott T.
출원인 / 주소
  • Artisan Components, Inc.
대리인 / 주소
    Martine Penilla & Kim, LLP
인용정보 피인용 횟수 : 32  인용 특허 : 25

초록 ▼

A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordl

대표청구항 ▼

[ What is claimed is:] [1.] A memory circuit, comprising:a memory core having an array of core cells, the array of core cells being coupled to a plurality of wordlines and a plurality of bitline pairs; anda self-timing path having a model core cell that is coupled to a model wordline that is driven

이 특허에 인용된 특허 (25) 인용/피인용 타임라인 분석

  1. Pascucci Luigi (Giovanni ITX) Olivo Marco (Bergamo ITX), Anti-noise and auto-stand-by memory architecture.
    상세보기
  2. Pascucci Luigi,ITX ; Olivo Marco,ITX, Anti-noise and auto-stand-by memory architecture.
    상세보기
  3. Pinkham Ray ; Yeo Cheow F., Block write power reduction memory with reduced power consumption during block write mode.
    상세보기
  4. Yero Emilio (Aix-en-Provence FRX), Current detection circuit for reading a memory in integrated circuit form.
    상세보기
  5. Kwon Gyu Wan (Kyungki-Do KRX), Electrically erasable programmable read only memory.
    상세보기
  6. Mann Eric N. (Issaquah WA), Eprom bit-line interface for implementing programming, verification and testing.
    상세보기
  7. Priebe Gordon W. (Champlin MN) Passow Robin H. (Maple Plain MN), Fast memory sense system.
    상세보기
  8. Kornachuk Steve P. ; Becker Scott T., High speed memory output circuitry and methods for implementing same.
    상세보기
  9. Sasaki Katsuro (Fuchu JPX) Moriwaki Nobuyuki (Kodaira JPX) Honjo Shigeru (Otsuki JPX) Nakamura Hideaki (Kodaira JPX), High speed semiconductor memory having a direct-bypass signal path.
    상세보기
  10. Chung, David Siu Fu, Intelligent memory architecture.
    상세보기
  11. Curd Derek R. (San Jose CA), Latching sense amplifier for a programmable logic device.
    상세보기
  12. Hikichi Hiroshi (Tokyo JPX), Memory device with current path cut-off circuit for sense amplifier.
    상세보기
  13. Passow Robin H. (Maple Plain MN) Priebe Gordon W. (Champlin MN) Isliefson Ronald D. (Lakeville MN) Mactaggart I. Ross (Eden Prairie MN) LeClair Kevin R. (Prior Lake MN), Method and apparatus for a low power self-timed memory control system.
    상세보기
  14. Hamada Minoru (Ogaki JPX) Ando Hitoshi (Gifu-ken JPX), Method of operating the semiconductor memory storing analog data and analog data storing apparatus.
    상세보기
  15. Lappington ; John P., Programmable read only memory for electronic engine control.
    상세보기
  16. Nakai Hiroto (Kawasaki JPX) Iwahashi Hiroshi (Yokohama JPX) Hiraga Nobuaki (Yokohama JPX), Semiconductor integrated circuit.
    상세보기
  17. Okubo Hiizu (Nishinomiya JPX), Semiconductor memory apparatus with internal synchronization.
    상세보기
  18. Abe Kazuhiko (Tokyo JPX), Semiconductor memory device.
    상세보기
  19. Matsumoto Naoki (Tokyo JPX) Wtanabe Yuji (Kawasaki JPX) Ohshima Shigeo (Yokohama JPX), Semiconductor memory device.
    상세보기
  20. Ohshima Shigeo,JPX, Semiconductor memory device having a plurality of banks.
    상세보기
  21. Yamasaki Kazuyuki (Tokyo JPX) Nishizaka Teiichiro (Tokyo JPX) Otsuki Kazutaka (Tokyo JPX), Semiconductor memory having a plurality of memory banks and sub-bit lines which are connected to a main bit line via MOS.
    상세보기
  22. Hamano Takahiro (Yamato) Matsui Masataka (Tokyo) Sato Katsuhiko (Yokohama), Semiconductor memory having an operation margin against a write recovery time.
    상세보기
  23. Pascucci Luigi (Sesto San Giovanni ITX), Sense circuit for storage devices such a non-volatile memories, with enhanced sensing discrimination.
    상세보기
  24. Nitta Yasuhiko,JPX ; Tsukude Masaki,JPX, Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays.
    상세보기
  25. Komarek James A. (Balboa Beach CA) Tanner Scott B. (Irvine CA) Padgett Clarence W. (Westminster CA) Minney Jack L. (Irvine CA), VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines.
    상세보기

이 특허를 인용한 특허 (32) 인용/피인용 타임라인 분석

  1. Brown, Jeffrey S., Address transition detect control circuit for self timed asynchronous memories.
    상세보기
  2. DeMaris, James E.; Eby, Michael D., Adjustable memory self-timing circuit.
    상세보기
  3. Abdollahi-Alibeik, Shahram; Huang, Chaofeng, Apparatus and method for producing an output clock pulse and output clock generator using same.
    상세보기
  4. Abdollahi Alibeik,Shahram; Huang,Chaofeng, Apparatus and method for producing dummy data and output clock generator using same.
    상세보기
  5. Abdollahi Alibeik,Shahram; Huang,Chaofeng, Architecture and method for output clock generation on a high speed memory device.
    상세보기
  6. Abdollahi-Alibeik, Shahram; Huang, Chaofeng, Delay line and output clock generator using same.
    상세보기
  7. Wu, Jiaqi; Lammers, Greg, Device enrollment in a cloud service using an authenticated application.
    상세보기
  8. James W. Wilkins, Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device.
    상세보기
  9. Wilkins, James W., Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device.
    상세보기
  10. Shin Jin-Uk Luke ; Osada Kenichi,JPX ; Khan Masood, Duplicate bitline self-time technique for reliable memory operation.
    상세보기
  11. Ghosh, Prokash; Roy, Sourav; Raj, Neha, Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof.
    상세보기
  12. Wu, Jiaqi; Lammers, Greg, Identity management and device enrollment in a cloud service.
    상세보기
  13. Becker, Scott T., Memories having reduced bitline voltage offsets.
    상세보기
  14. Goetz, Marco; Ben Ari, Nimrod, Memory device architecture and method for improved bitline pre-charge and wordline timing.
    상세보기
  15. Trivedi, Manish; Rao, Setti Shanmukheswara; Goel, Ankur, Memory device with control circuitry for generating a reset signal in read and write modes of operation.
    상세보기
  16. Trivedi, Manish; Rao, Setti Shanmukheswara; Goel, Ankur, Memory device with separately controlled sense amplifiers.
    상세보기
  17. Jetton, Mark W.; Childs, Lawrence F.; Lu, Olga R.; Starnes, Glenn E., Memory having a dummy bitline for timing control.
    상세보기
  18. Moyer, William C.; Pelley, III, Perry H., Memory having sense time of variable duration.
    상세보기
  19. Arsovski, Igor; Dobson, Daniel A.; Hebig, Travis R., Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system.
    상세보기
  20. Bachot, Jean-Marc Philippe; Badi, Eric, Method and apparatus for accessing a memory core multiple times in a single clock cycle.
    상세보기
  21. Bachot,Jean Marc; Badi,Eric, Method and apparatus for accessing a memory core multiple times in a single clock cycle.
    상세보기
  22. Becker, Scott T., Methods for reducing bitline voltage offsets in memory devices.
    상세보기
  23. Arsovski, Igor; Braceras, George Maria; Houle, Robert M.; Pilo, Harold, SRAM delay circuit that tracks bitcell characteristics.
    상세보기
  24. Qiu, Yunchen; Toops, David J.; Davis, Harold L., Self-latch sense timing in a one-time-programmable memory architecture.
    상세보기
  25. Starnes, Glenn E., Self-timed memory having common timing control circuit and method therefor.
    상세보기
  26. Brown Jeffrey S., Self-timing circuit for semiconductor memory devices.
    상세보기
  27. Onizawa, Tadashi; Midorikawa, Tsuyoshi; Hayakawa, Shigeyuki; Tanaka, Yutaka, Semiconductor integrated circuit device.
    상세보기
  28. Ishii Toshiji,JPX, Semiconductor memory device with dummy word line.
    상세보기
  29. Maki,Yasuhiko; Uetake,Toshiyuki, Semiconductor memory including self-timing circuit.
    상세보기
  30. Becker Scott T. ; Rao Venkata N., Slew tolerant clock input buffer and a self-timed memory core thereof.
    상세보기
  31. Kodama, Tsuyoshi, Static memory having self-timing circuit.
    상세보기
  32. Lowrey, Tyler; Parkinson, Ward D.; Bedeschi, Ferdinando; Resta, Claudio; Gastaldi, Roberto; Casagrande, Giulio, Using a bit specific reference level to read a resistive memory.
    상세보기

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로