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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0918203 (1997-08-25) |
| 발명자 / 주소 |
|
| 출원인 / 주소 |
|
| 대리인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 588 인용 특허 : 38 |
A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical bl
A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block. Wear-leveling is performed on a block being written when both total and incremental counts exceed system-wide total and incremental thresholds. The incremental-write count is cleared after a block is wear-leveled, but the total-write count is never cleared. The incremental-write count prevents moving a block again immediately after wear-leveling. The thresholds are adjusted as the system ages to provide even wear.
[ What is claimed is:] [1.] A unified re-mapping table for a flash-memory system, the unified re-mapping table comprising:a plurality of entries, an entry in the plurality of entries selected by a logical address from a host system, each entry in the plurality of entries having:a physical-block-addr
[ What is claimed is:] [1.] A unified re-mapping table for a flash-memory system, the unified re-mapping table comprising:a plurality of entries, an entry in the plurality of entries selected by a logical address from a host system, each entry in the plurality of entries having:a physical-block-address field containing a physical block address of a block in an array of flash-memory devices, each flash-memory device containing non-volatile storage cells that retain data when a power supply is no longer applied to the flash-memory device;a total-write-counter field for indicating a total number of write-erase cycles of the block identified by the physical-block-address field;an incremental-write-counter field for indicating an incremental number of write-erase cycles since a wear-leveling operation for the block;wherein both the total number and the incremental number from the entry must exceed thresholds to initiate wear-leveling for the block;wherein the block is wear-leveled by moving the physical block address and the total number to a different entry in the unified re-mapping table when data is exchanged between blocks,wherein the flash-memory system further comprises:a total-threshold resister containing a total-write threshold for the flash-memory system;an incremental-threshold register containing an incremental-write threshold for the flash-memory system;total compare means, coupled to the total-threshold register and receiving the total number from the entry selected by a current logical address, for activating a first signal when the total number from the entry in the unified re-mapping table exceeds the total-write threshold;incremental compare means, coupled to the incremental-threshold register and receiving the incremental number from the entry selected by the current logical address, for activating a second signal when the incremental number from the entry in the unified re-mapping table exceeds the incremental-write threshold;wear-leveling means, activated by a write to the current logical address when both the first signal and the second signal are activated, for wear-leveling the block by moving the physical block address and the total number to a different entry in the unified re-mapping table, and for replacing the physical block address with a new physical block address for a physical block having a smaller total number of write-erase cycles, reby the total number from the entry must exceed the total-write threshold and the incremental number must exceed the incremental-write threshold to initiate wear-leveling and whereby each entry includes the physical block address for address translation to the flash-memory devices and two write-counters for wear-leveling.
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