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Low temperature BPSG deposition process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
  • H01L-021/469
출원번호 US-0671021 (1996-06-25)
발명자 / 주소
  • Ajmera Atul C.
  • Gambino Jeffrey Peter
  • Nguyen Son Van
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Schmeiser, Olsen & Watts
인용정보 피인용 횟수 : 25  인용 특허 : 17

초록

A process for the low temperature deposition of a thin film of borophosphosilicate glass ("BPSG") for use in semiconductor devices, such as DRAMs, is disclosed. The process includes utilizing R--OH groups as reagents to provide additional --OH groups so that an intermediate {Si(OH).sub.4 }.sub.n is

대표청구항

[ We claim:] [1.] A process comprising the steps of:a) depositing an initial thin film of doped silicon oxide onto a semiconductor structure at a temperature of less than 750.degree. C.;b) annealing the initial thin film of doped silicon oxide in situ; andc) depositing a final thin film of doped sil

이 특허에 인용된 특허 (17)

  1. Peters John W. (Malibu CA), Low temperature process for depositing oxide layers by photochemical vapor deposition.
  2. Kim Changgyu (Suwon KRX) Hong Changki (Suwon KRX) Chung Uin (Suwon KRX) Ahn Yongchul (Ahnyang KRX), Method for fabricating an interlayer-dielectric film of a semiconductor device by using a plasma treatment prior to refl.
  3. Lee Peter W. (Fremont CA) Wang David N. K. (Saratoga CA) Nagashima Makoto (Machida JPX) Fukuma Kazuto (Osaka JPX) Sato Tetsuya (Narita JPX), Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer.
  4. Nishimura Yukuo (Sagamihara JPX) Eguchi Ken (Yokohama JPX) Matsuda Hiroshi (Yokohama JPX) Haruta Masahiro (Funabashi JPX) Hirai Yutaka (Tokyo JPX) Nakagiri Takashi (Tokyo JPX), Method for forming a deposited film.
  5. Maeda Kazuo (Tokyo JPX) Tokumasu Noboru (Tokyo JPX) Nishimoto Yuko (Tokyo JPX), Method for manufacturing a semiconductor device.
  6. Thakur Randir P. S. (Boise ID) Gonzalez Fernando (Boise ID), Method for optimizing thermal budgets in fabricating semiconductors.
  7. Suntola Tuomo S. (Espoo FIX) Pakkala Arto J. (Espoo FIX) Lindfors Sven G. (Espoo FIX), Method for performing growth of compound thin films.
  8. Ushikawa Harunori (Kofu JPX), Method of forming a phosphorus doped silicon film.
  9. Park Cheol-Soo (Kyoungki KRX) Koh Yo-Hwan (Seoul KRX) Park Jae-Beom (Seoul KRX) Park Young-Jin (Kyoungki KRX) Oh Jin-Seong (Seoul KRX), Method of manufacturing a contact of a highly integrated semiconductor device.
  10. Bouffard Mark D. (Westford VT) King William J. (Jericho VT) Martin Cheryl M. (Essex Junction VT), PECVD process for forming BPSG with low flow temperature.
  11. Miyasaka Mitsutoshi (Suwa JPX) Little Thomas W. (Suwa JPX), Process for fabricating a thin film semiconductor device.
  12. Maeda Kazuo (Tokyo JPX) Tokumasu Noboru (Tokyo JPX) Nishimoto Yuko (Tokyo JPX), Process for forming CVD film and semiconductor device.
  13. Tsukune Atuhiro (Kawasaki JPX) Furumura Yuji (Kawasaki JPX) Masanobu Hatanaka (Kawasaki JPX), Process for forming silicon oxide film.
  14. Yamagata Kenji (Kawasaki JPX) Yonehara Takao (Atsugi JPX), Process of fabricating a semiconductor substrate.
  15. Okuyama Yasushi (Tokyo JPX) Saitoh Manzoh (Tokyo JPX), Semiconductor device having improved multi-layer structure of insulating film and conductive film.
  16. Monkowski Joseph R. (Danville CA) Logan Mark A. (Leucadia CA) Wright Lloyd F. (Carlsbad CA), Simultaneous glass deposition and viscoelastic flow process.
  17. Liu Charles C. (Mt. View CA) Nauka Krzysztof (Mt. View CA), Suppression of water vapor absorption in glass encapsulation.

이 특허를 인용한 특허 (25)

  1. Pan,Qi; Li,Jiutao; Hu,Yongjun Jeff; McTeer,Allen, Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines.
  2. Derderian,Garo J.; Hill,Chris W., Method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry.
  3. Derderian,Garo J.; Hill,Chris W., Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry.
  4. Derderian,Garo J.; Hill,Chris W., Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry.
  5. Derderian,Garo J.; Hill,Chris W., Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry.
  6. Li,Weimin; Sandhu,Gurtej S., Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry, methods of forming trench isolation in the fabrication of integrated circuitry, methods of depositing silicon dioxide-comprising layers in the fabrication of integrated circuitry, and methods of forming bit line over capacitor arrays of memory cells.
  7. Derderian,Garo J.; Hill,Chris W., Method of forming trench isolation in the fabrication of integrated circuitry.
  8. Vaartstra,Brian A., Method of forming trench isolation in the fabrication of integrated circuitry.
  9. Jung, Woo-Chan; Jeon, Jin-Ho; Lim, Jeon-Sig; Yi, Jong-Seung, Method of manufacturing insulating layer and semiconductor device including insulating layer.
  10. Li,Weimin; Sandhu,Gurtej S., Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells.
  11. Vaartstra,Brian A., Methods of forming a phosphorous doped silicon dioxide comprising layer.
  12. Vaartstra, Brian A., Methods of forming a phosphorus doped silicon dioxide-comprising layer.
  13. Zhang,Jianping, Methods of forming integrated circuitry.
  14. Ho, Yunjun; Gilgen, Brent, Methods of forming silicon oxides and methods of forming interlevel dielectrics.
  15. Ho, Yunjun; Gilgen, Brent, Methods of forming silicon oxides and methods of forming interlevel dielectrics.
  16. Patraw, Robert D.; Roberts, M. Ceredig; Cook, Keith R., Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry.
  17. Patraw, Robert D.; Roberts, Martin Ceredig; Cook, Keith R., Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry.
  18. Sandhu,Gurtej S., Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry.
  19. Sandhu,Gurtej S., Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry.
  20. Sandhu,Gurtej S., Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry.
  21. Sandhu,Gurtej S., Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry.
  22. Sandhu,Gurtej S.; Patraw,Robert D.; Roberts,M. Ceredig; Cook,Keith R., Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry.
  23. Doan,Trung Tri; Sandhu,Gurtej S., Methods of forming trench isolation regions.
  24. Jung,Woo Chan; Jeon,Jin Ho; Lim,Jeon Sig; Yi,Jong Seung, Semiconductor device including insulating layer.
  25. Ahn, Sang Tae; Sheen, Dong Sun; Song, Seok Pyo; Shin, Jong Han, Semiconductor device with flowable insulation layer formed on capacitor and method for fabricating the same.
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