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Semiconductor device with refractory metal element 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/80
  • H01L-031/0328
  • H01L-031/112
출원번호 US-0837458 (1997-04-18)
우선권정보 JP-0309168 (1996-11-20)
발명자 / 주소
  • Oku Tomoki,JPX
  • Yoshida Naohito,JPX
  • Miyakuni Shinichi,JPX
  • Shiga Toshihiko,JPX
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha, JPX
대리인 / 주소
    Leydig, Voit & Mayer Ltd
인용정보 피인용 횟수 : 59  인용 특허 : 7

초록

A semiconductor device includes a self-aligned refractory metal constituent in a recess in a semiconductor substrate and having the same plane pattern as a bottom surface of the recess. The width of the constituent is determined by the plane pattern of the recess and, accordingly, the pattern width

대표청구항

[ What is claimed is:] [1.] A semiconductor device comprising:a semiconductor substrate having a surface and a recess at the surface, the recess having a bottom surface and side walls transverse to the bottom surface, the semiconductor substrate further comprising a channel region at the bottom surf

이 특허에 인용된 특허 (7)

  1. Nakanishi Mamiko,JPX, Field effect transistor.
  2. Arima Hideaki (Hyogo JPX) Ajika Natsuo (Hyogo JPX), MIS-type semiconductor device of LDD structure and manufacturing method thereof.
  3. Oku Tomoki,JPX ; Miyakuni Shinichi,JPX ; Kasai Nobuyuki,JPX ; Kohno ; deceased Yasutaka,JPX ITX by Yoko Kohno ; heir/legal representative, Method of fabricating semiconductor device.
  4. Besson Raymond J. (Besancon FRX), Piezoelectric resonator.
  5. Ando Yuji (Tokyo JPX), Schottky gate field effect transistor.
  6. Kuwata Nobuhiro (Yokohama JPX), Semiconductor device and a method for fabricating the same.
  7. Tehrani Saied N. ; Huang Jenn-Hwa ; Goronkin Herbert ; Schirmann Ernest ; Martinez Marino J., Stable FET with shielding region in the substrate.

이 특허를 인용한 특허 (59)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Kikkawa, Toshihide, Compound semiconductor device.
  4. Kikkawa, Toshihide, Compound semiconductor device.
  5. Kikkawa, Toshihide, Compound semiconductor device.
  6. Kikkawa, Toshihide, Compound semiconductor device and method for fabricating the same.
  7. Kikkawa, Toshihide, Compound semiconductor device and method for fabricating the same.
  8. Pohjonen, Helena, Crystal-less oscillator transceiver.
  9. Oppermann, Klaus-Guenter, Device and method for reducing a voltage dependent capacitive coupling.
  10. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  11. Kazuhiko Onda JP, Field effect transistor and method of manufacturing thereof.
  12. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  21. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  22. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  23. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  24. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  26. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  27. Nunokawa Mitsuji,JPX ; Sato Yutaka,JPX, Method of forming a semiconductor device having a barrier layer interposed between the ohmic contact and the schottky contact.
  28. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  29. Aigner, Robert; Elbrecht, Lüder; Marksteiner, Stephan; Nessler, Winfried, Method of producing a topology-optimized electrode for a resonator in thin-film technology.
  30. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  31. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  32. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  33. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  34. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  35. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  38. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  39. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  40. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  41. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  42. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  43. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  44. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  45. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  46. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  47. Inumiya, Seiji; Saito, Tomohiro; Yagishita, Atsushi; Hieda, Katsuhiko; Iinuma, Toshihiko, Semiconductor device with groove type channel structure.
  48. Kao Dah-Bin ; Hoang Loc B. ; Wu Albert T. ; Chan Tung-Yi, Semiconductor memory array with buried drain lines and processing methods therefor.
  49. Kao Dah-Bin ; Hoang Loc B. ; Wu Albert T. ; Chan Tung-Yi, Semiconductor memory array with buried drain lines and processing methods therefor.
  50. Brunn, Brian T.; Seemann, Brian K., Skew lots for IC oscillators and other analog circuits.
  51. Brunn, Brian T.; Seemann, Brian K., Skew lots for IC oscillators and other analog circuits.
  52. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  53. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  54. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  55. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  56. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  57. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  58. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  59. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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