초록 ▼

A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured

A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets and associated control information are forwarded, if necessary given the network topology, through a separate outbound subsystem. When packets traverse the internal links from one subsystem to another, encapsulation operations are conducted such as appending an additional cyclic redundancy code (CRC) to the packet before going through the internal link.

대표청구항 ▼

[ What is claimed is:] [1.] In a switch comprising a plurality of switch elements, an apparatus for selectively performing header field replacement of packets communicated between two switch elements, comprising:a cascading output process (COP) located in a first switch element and configured to rec

[ What is claimed is:] [1.] In a switch comprising a plurality of switch elements, an apparatus for selectively performing header field replacement of packets communicated between two switch elements, comprising:a cascading output process (COP) located in a first switch element and configured to receive a packet, said packet comprising a header, data and cycle redundancy code (CRC), said COP further configured to receive control information and modify the packet by prepending control information to the packet, said control information providing information regarding a type of the packet, said COP further configured to output the modified packet;an output interface located in the first switch element, said output interface coupled to receive the modified packet and is configured to selectively generate a CRC to append to the modified packet, said output interface further configured to output the modified packet;an input interface located in a second switch element and configured to receive the packet output by the output interface of the first switch element, check frame validity of the packet using the appended CRC, and strip the appended CRC from the packet;a cascading input process (CIP) located in the second switch element and coupled to the input interface, said CIP configured to strip the control information to provide the control information to the second switch element to enable the second switch element to selectively modify the header of the packet in accordance with the control information prior to output from the second switch element.