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Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0731455 (1996-10-18)
발명자 / 주소
  • Mohamed Moataz Ali
출원인 / 주소
  • Samsung Electronics Co., Ltd., KRX
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin & FrielMarino
인용정보 피인용 횟수 : 68  인용 특허 : 11

초록

The present invention provides a new programming language which. is a superset of C++ optimized for writing vectorized dual-threaded programs on the MSP media processor. This invention discloses novel language constructs in the syntax and semantics to facilitate efficient programming and the generat

대표청구항

[ I claim:] [1.] A method for creating a computer program on a computer readable media for execution by a vector processor, the method comprising:a computer system reading a computer program written in a superset of C programming language, wherein the C programming language defines a plurality of op

이 특허에 인용된 특허 (11)

  1. Kohler Joylee E. (Broomfield CO) Mathews Eugene P. (Barrington IL) Nalbone Robert D. (Thornton CO) Palmer Craig F. (Arvada CO), Automatic call distribution based on matching required skills with agents skills.
  2. Sakamura Ken (Tokyo JPX), Data processor.
  3. Lahti Archie E. (Fridley MN) James Ralph L. (Andovor MN) Byers Larry L. (Apple Valley MN), Macro level control of an activity switch in a scientific vector processor which processor requires an external executiv.
  4. Iwasawa Kyoko (Tokyo JPX) Tanaka Yoshikazu (Saitama JPX), Method for converting a source program of high level language statement into an object program for a vector processor.
  5. Kanada Yasusi (Tokyo JPX) Torii Shunichi (Musashino JPX) Kojima Keiji (Kokubunji JPX), Method for determining whether data signals of a first set are related to data signal of a second set.
  6. Cutler David N. (Bellevue WA) Orbits David A. (Redmond WA) Bhandarkar Dileep (Shrewsbury MA) Cardoza Wayne (Merrimack NH) Witek Richard T. (Littleton MA), Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simulta.
  7. Scheuneman James H. (St. Paul MN), Multiple unit adapter.
  8. Stokes ; Richard Arthur ; Kuck ; David Jerome ; Jensen ; Carl Anton, Scientific processor.
  9. Vasilevsky Alexander D. (Watertown MA) Sabot Gary W. (Cambridge MA) Lasser Clifford A. (Cambridge MA) Tennies Lisa A. (Bedford MA) Weinberg Tobias M. (Somerville MA) Seamonson Linda J. (Wellesley MA), System and method for compiling a fine-grained array based source program onto a course-grained hardware.
  10. Rusterholz John T. (Roseville MN) Homan Charles J. (St. Paul MN) Brown Lowell E. (Anoka MN) Bennett Donald B. (Burnsville MN) Malnati Robert J. (St. Paul MN) Hamstra James R. (Plymouth MN), Tightly coupled scientific processing system.
  11. Kinoshita Yoshiaki (Hadano JPX) Kazama Yoshiharu (Hadano JPX) Takamine Yoshio (Kokubunji JPX), Vector processor.

이 특허를 인용한 특허 (68)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
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  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
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  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Goodwin, David William; Maydan, Dror; Chen, Ding-Kai; Petkov, Darin Stamenov; Tjiang, Steven Weng-Kiang; Tu, Peng; Rowen, Christopher, Automatic instruction set architecture generation.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
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  21. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  23. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  26. Boehm,Fritz A., Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index.
  27. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  28. Johnson, William M., Hardware instruction generation unit for specialized processors.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
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  33. Hartono, Albert; Bharadwaj, Jayashankar; Vasudevan, Nalini; Baghsorkhi, Sara S.; Lee, Victor W.; Kim, Daehyun, Instruction to reduce elements in a vector register with strided access pattern.
  34. Beadle, Bruce Anthony; Brown, Michael Wayne; Paolini, Michael Anthony; Rothert, Douglas Scott, JIT/compiler Java language extensions to enable field performance and serviceability.
  35. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
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  37. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  38. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Memory access consolidation for SIMD processing elements using transaction identifiers.
  39. Ansari, Ahmad R., Method and apparatus for transferring vector data between memory and a register file.
  40. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  41. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
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  51. Tserng,Christopher, Method for scheduling processors and coprocessors with bit-masking.
  52. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
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  56. Hosek, Martin; Moura, Jairo Terra; Elmali, Hakan, Observer-corrector control system for systems with unmodeled dynamics.
  57. Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Parallel data processing apparatus.
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  60. Lakhotia, Arun; Karim, Md. Enamul; Walenstein, Andrew, Phylogeny generation.
  61. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  62. Barlow, Stephen; Bailey, Neil; Ramsdale, Timothy; Plowman, David; Swann, Robert, Register file with separate registers for compiler code and low level code.
  63. Paver, Nigel C.; Aldrich, Bradley C., SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags.
  64. Master,Paul L.; Watson,John, Storage and delivery of device features.
  65. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  66. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  67. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  68. Glossner, III, Clair John; Hokenek, Erdem; Meltzer, David; Moudgill, Mayan, Vector register file with arbitrary vector addressing.
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