초록 ▼

A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor inclu

A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.

대표청구항 ▼

[ What is claimed is:] [1.] A vertical transistor comprising:a first insulation layer overlying a semiconductor substrate;a first conductive layer overlying said first insulation layer:a second insulation layer pattern overlying said first conductive layer, said second insulation layer pattern havin

[ What is claimed is:] [1.] A vertical transistor comprising:a first insulation layer overlying a semiconductor substrate;a first conductive layer overlying said first insulation layer:a second insulation layer pattern overlying said first conductive layer, said second insulation layer pattern having a first contact hole;a gate electrode comprising a second conductive layer overlying said second insulation layer pattern, said gate electrode having a hole which is concentric with and has a diameter larger than said first contact hole, thereby exposing said first conductive layer at the bottom of said contact hole;a third insulation layer pattern overlying said gate electrode, said third insulation layer pattern having a second contact hole which is concentric with and approximately the same size as said first contact hole;gate insulation comprising a fourth insulation layer, said gate insulation formed on an inner sidewall of said gate electrode hole, thereby forming a gate insulation hole;a third conductive layer pattern filling each of said first contact hole, said second contact hole, and said gate insulation hole, said third conductive layer pattern having a drain region, a source region, and a channel region positioned between said drain and source regions;said drain region formed substantially in said first contact hole and connected to said first conductive layer;said source region formed substantially in said second contact hole and connected to a source electrode, said source electrode consisting of a fourth conductive layer formed on said third insulation layer pattern and on said second contact hole; andsaid channel region formed substantially in said gate insulation hole between said source and drain regions.