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Thick plated interconnect and associated auxillary interconnect 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0992282 (1997-12-17)
발명자 / 주소
  • Efland Taylor R.
  • Mai Quang X.
  • Williams Charles E.
  • Keller Stephen A.
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    McLarty
인용정보 피인용 횟수 : 85  인용 특허 : 6

초록

A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The bar

대표청구항

[ What is claimed is:] [1.] A semiconductor device, comprising:a thick plated interconnect, comprising:a section of a copper seed layer;a copper lead over the section of the copper seed layer;a bonding cap coupled to the copper lead, comprising:a barrier member formed from a section of a barrier lay

이 특허에 인용된 특허 (6)

  1. Farooq Mukta Shaji ; Kaja Suryanarayana ; Perfecto Eric Daniel ; White George Eugene, Capped copper electrical interconnects.
  2. Efland Taylor R. (Richardson TX) Malhi Satwinder (Garland TX) Smayling Michael C. (Missouri City TX) Devore Joseph A. (Dallas TX) Teggatz Ross E. (Dallas TX) Morton Alec J. (Plano TX), Device having current ballasting and busing over active area using a multi-level conductor process.
  3. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
  4. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  5. Hasegawa Makiko,JPX ; Toyoda Yoshihiko,JPX ; Mori Takeshi,JPX ; Fukada Tetsuo,JPX, Multilevel embedded wiring system.
  6. Kondo Ichiharu (Nagoya JPX) Noritake Chikage (Ama-gun JPX) Watanabe Yusuke (Obu JPX), Semiconductor device with bump structure.

이 특허를 인용한 특허 (85)

  1. Nikhil Vishwanath Kelkar ; Stephen A. Gee, Barrier pad for wafer level chip scale packages.
  2. Huang,Min Lung, Bump electrodes having multiple under ball metallurgy (UBM) layers.
  3. Lin,Mou Shiung, Chip structure with redistribution traces.
  4. Shiu, Jian-Bin; Lee, Tung-Sheng, Conductive pad structure and method of fabricating the same.
  5. Naem, Abdalla Aly, Copper-compatible fuse target.
  6. Naem, Abdalla Aly; Razouk, Reda, Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure.
  7. Too, Elena H.; Gerst, Paul R.; Paneccasio, Jr., Vincent; Hurtubise, Richard W., Electroplating chemistry for the CU filling of submicron features of VLSI/ULSI interconnect.
  8. Tanimoto,Satoshi, Heat resistant ohmic electrode and method of manufacturing the same.
  9. Tanimoto,Satoshi, Heat resistant ohmic electrode and method of manufacturing the same.
  10. Lin, Mou-Shiung, High performance IC chip having discrete decoupling capacitors attached to its IC surface.
  11. Rueb,Michael; Detzel,Thomas, Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric.
  12. Rieger, Johann; Lipp, Stefan; Zeindl, Hans Peter; Detzel, Thomas; Maier, Hubert, Method for forming an integrated semiconductor circuit arrangement.
  13. Li Weipang ; Tummala Rao R., Method for manufacturing a multilayer wiring substrate.
  14. Naem, Abdalla Aly, Method of forming a copper topped interconnect structure that has thin and thick copper traces.
  15. Jao-Chin Cheng TW; Chang-Chin Hsieh TW; Chih-Peng Fan TW; Chin-Chung Chang TW, Method of forming micro-via.
  16. Wang,James Jen Ho; Poarch,Justin E., Multi-chips semiconductor device assemblies and methods for fabricating the same.
  17. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  23. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  24. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  25. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  26. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  27. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  28. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  29. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  31. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  32. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  33. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  34. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  35. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  36. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  37. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  38. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  39. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  41. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  42. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  43. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  44. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  45. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  46. Uzoh Cyprian E., Process for forming a copper-containing film.
  47. Sun, Sey-Shing; Pallinti, Jayanthi; Vijay, Dilip; Bhatt, Hemanshu; Ying, Hong; Kao, Chiyi; Burke, Peter, Reduction of macro level stresses in copper/low-K wafers.
  48. Hatano,Keisuke; Abiru,Takahisa, Semiconductor device.
  49. Yasuda Hidefumi,JPX ; Tomita Mayumi,JPX, Semiconductor device and fabrication method thereof.
  50. Lin, Li-Jen; Murphy, Stephen A.; Sun, Wei, Semiconductor device and method of forming a dual UBM structure for lead free bump connections.
  51. Lin, Li-Jen; Murphy, Stephen A.; Sun, Wei, Semiconductor device and method of forming a dual UBM structure for lead free bump connections.
  52. Wada, Tamaki; Tobita, Akihiro; Ichihara, Seiichi, Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electrode edge spacing.
  53. Hu, Yu-Shan, Semiconductor packaging structure having stacked seed layers.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  61. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  62. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  63. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  70. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  71. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  72. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  73. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  74. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  75. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  76. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  77. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  78. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  79. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  80. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  81. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  82. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  83. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  84. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  85. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
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