초록 ▼

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The mo

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

대표청구항 ▼

[ What is claimed is:] [1.] A bit line hierarchy structure for a plurality of memory sub-arrays, comprising:a plurality of first hierarchy bit lines, each first hierarchy bit line being associated with a given memory sub-array of the plurality of memory sub-arrays;a plurality of second hierarchy bit

[ What is claimed is:] [1.] A bit line hierarchy structure for a plurality of memory sub-arrays, comprising:a plurality of first hierarchy bit lines, each first hierarchy bit line being associated with a given memory sub-array of the plurality of memory sub-arrays;a plurality of second hierarchy bit lines, each second hierarchy bit line being associated with a different respective grouping of memory sub-arrays of the plurality of memory sub-arrays, each second hierarchy bit line partially overlapping at least one other second hierarchy bit line wherein the respective groupings of memory sub-arrays of said each second hierarchy bit line and said one other second hierarchy bit line share a common memory sub-array; andselective multiplexer means provided with each memory sub-array for selectively coupling said each memory sub-array to at least one of its associated first and second hierarchy bit lines.