초록 ▼

A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains

A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains connected within the buffer circuit. The buffer circuit retains the benefits of the split-drive, dual output transistor configuration, and also substantially improves circuit gain per delay gate by connecting the weighted static gain chains between pulse generators and output transistors of the buffer circuit. The gain chains are designed to rapidly propagate the edge that fires their respective output transistors but slowly propagate the edge that turns the output transistor off, by reducing the devices that propagate the shut-off transition. N-type and p-type devices within the buffer circuit are arranged and sized to promote the gain characteristic of the split drive buffer circuit.

대표청구항 ▼

[ What is claimed is:] [1.] A buffer circuit for receiving an input signal at a buffer input terminal and providing an output signal at a buffer output terminal, said buffer circuit comprising:a first pulse generator arranged for receiving said input signal, said first pulse generator being responsi

[ What is claimed is:] [1.] A buffer circuit for receiving an input signal at a buffer input terminal and providing an output signal at a buffer output terminal, said buffer circuit comprising:a first pulse generator arranged for receiving said input signal, said first pulse generator being responsive to a rising edge of said input signal for providing a first pulse signal;a second pulse generator arranged for receiving said input signal, said second pulse generator being responsive to a falling edge of said input signal for providing a second pulse signal;a first gain chain circuit connected to said first pulse generator;a first output switching device connected to said first gain chain circuit, said first output switching device being responsive to said first pulse signal for connecting said buffer output terminal to a first voltage level;a second gain chain circuit connected to said second pulse generator;a second output switching device connected to said second gain chain circuit, said second output switching device being responsive to said second pulse signal for connecting said buffer output terminal to a second voltage level; anda holding circuit connected between said buffer input terminal and said buffer output terminal.