[특허]Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

[미국특허] Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-007/00
출원번호	US-0248194 (1999-02-10)
발명자 / 주소	Baker Russel Jacob Manning Troy A.
출원인 / 주소	Micron Technology, Inc.
대리인 / 주소	Dorsey & Whitney LLP
인용정보	피인용 횟수 : 201 인용 특허 : 115

초록 ▼

A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets of the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evaluation circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device.

대표청구항 ▼

[ We claim:] [1.] A method of adaptively adjusting the phase of an internal clock signal, the method comprising:receiving a digital signal having a plurality of transitions;comparing transitions of the digital signal to transitions of the internal clock signal at different phases of the internal clock signal;determining respective delay times of the digital signal relative to the internal clock signal based on each of the comparisons;identifying each phase of the internal clock signal that resulted in a delay time within a predetermined range of delay times;selecting one of the identified phases of the internal clock signal; andadjusting the phase of the internal clock signal to the selected phase of the internal clock signal.

이 특허에 인용된 특허 (115) 인용/피인용 타임라인 분석

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Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
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Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
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Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
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Zohni, Wael O.; Schmidt, William L.; Smith, Michael John Sebastian; Plunkett, Jeremy Matthew, Embossed heat spreader.
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Zohni, Wael O.; Schmidt, William; Smith, Michael J. S.; Plunkett, Jeremy Matthew, Embossed heat spreader.
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Smith, Michael John Sebastian; Rajan, Suresh Natarajan; Wang, David T, Emulation of abstracted DIMMS using abstracted DRAMS.
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Smith, Michael J. S.; Rajan, Suresh Natarajan; Wang, David T., Emulation of abstracted DIMMs using abstracted DRAMs.
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Horowitz, Mark A.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Flash controller to provide a value that represents a parameter to a flash memory.
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Horowitz, Mark A.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Flash controller to provide a value that represents a parameter to a flash memory.
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Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Flash memory controller with calibrated data communication.
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Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
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Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
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Richardson,John G.; Morrison,John L.; Hawkes,Grant L., Induction heating apparatus and methods for selectively energizing an inductor in response to a measured electrical characteristic that is at least partially a function of a temperature of a material.
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Richardson,John G., Induction heating apparatus and methods of operation thereof.
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Horowitz, Mark A.; Barth, Richard M.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Integrated circuit device and signaling method with phase control based on information in external memory device.
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Horowitz, Mark A.; Barth, Richard M.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Integrated circuit device and signaling method with topographic dependent equalization coefficient.
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Horowitz,Mark A.; Barth,Richard M.; Hampel,Craig E.; Moncayo,Alfredo; Donnelly,Kevin S.; Zerbe,Jared L., Integrated circuit device that stores a value representative of a drive strength setting.
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Horowitz, Mark A.; Barth, Richard M.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices.
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Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Integrated circuit with timing adjustment mechanism and method.
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Horowitz,Mark A.; Barth,Richard M.; Hampel,Craig E.; Moncayo,Alfredo; Donnelly,Kevin S.; Zerbe,Jared L., Integrated circuit with transmit phase adjustment.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power saving operations during a command-related latency.
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Frans, Yohan Usthavia; Li, Simon, Levelization of memory interface for communicating with multiple memory devices.
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Kizer, Jade M, Locked loop circuit with clock hold function.
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Kizer, Jade M, Locked loop circuit with clock hold function.
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Kizer, Jade M., Locked loop circuit with clock hold function.
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Kizer, Jade M., Locked loop circuit with clock hold function.
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Kizer, Jade M.; Lau, Benedict C., Locked loop with dual rail regulation.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory apparatus operable to perform a power-saving operation.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation system and method with refresh capabilities.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation with power saving capabilities.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
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Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.
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Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.
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Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.
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Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.
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Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos; Tsern, Ely K.; Ware, Frederick A., Memory component with pattern register circuitry to provide data patterns for calibration.
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Horowitz, Mark A.; Barth, Richard M.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., Memory controller and method utilizing equalization co-efficient setting.
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Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Memory controller that calibrates a transmit timing offset.
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Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Memory controller with circuitry to set memory device-specific reference voltages.
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Tzou, Joseph; Tran, Thinh; Li, Jun, Memory device and method.
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Tzou, Joseph; Tran, Thinh; Li, Jun, Memory device and method.
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Horowitz,Mark A.; Barth,Richard M.; Hampel,Craig E.; Moncayo,Alfredo; Donnelly,Kevin S.; Zerbe,Jared L., Memory device having programmable drive strength setting.
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Hampel,Craig E.; Perego,Richard E.; Sidiropoulos,Stefanos S.; Tsern,Ely K.; Ware,Fredrick A., Memory device signaling system and method with independent timing calibration for parallel signal paths.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory device with emulated characteristics.
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Tran,Thinh; Tzou,Joseph; Parameswaran,Suresh, Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilites.
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Rajan, Suresh N.; Schakel, Keith R; Smith, Michael J. S.; Wang, David T; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
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Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory modules with reliability and serviceability functions.
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Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
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Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
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Lin,Feng; Keeth,Brent; Johnson,Brian; Lee,Seong hoon, Memory system and method for strobing data, command and address signals.
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Lin,Feng; Keeth,Brent; Johnson,Brian; Lee,Seong hoon, Memory system and method for strobing data, command and address signals.
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Lin,Feng; Keeth,Brent; Johnson,Brian; Lee,Seong hoon, Memory system and method for strobing data, command and address signals.
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Lin,Feng; Keeth,Brent; Johnson,Brian; Lee,Seong hoon, Memory system and method for strobing data, command and address signals.
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Lin,Feng; Keeth,Brent; Johnson,Brian; Lee,Seong hoon, Memory system and method for strobing data, command and address signals.
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Wang, David T.; Rajan, Suresh Natarajan, Memory system for synchronous data transmission.
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Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Memory system with calibrated data communication.
상세보기
Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Memory system with calibrated data communication.
상세보기
Zerbe, Jared LeVan; Donnelly, Kevin S.; Sidiropoulos, Stefanos; Stark, Donald C.; Horowitz, Mark A.; Yu, Leung; Vu, Roxanne; Kim, Jun; Garlepp, Bruno W.; Ho, Tsyr-Chyang; Lau, Benedict Chung-Kwong, Memory system with calibrated data communication.
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Keeth, Brent, Memory system with dynamic timing correction.
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Smith, Michael J. S.; Rajan, Suresh Natarajan, Memory systems and memory modules.
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Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory systems and memory modules.
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Cornelius, William; Taoyama, Minoru; Thompson, Paul, Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains.
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Cornelius,William; Taoyama,Minoru; Thompson,Paul, Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains.
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Eustis, Steven M.; Gorman, Kevin W.; Lackey, David E.; Ouellette, Michael R., Method and apparatus for a robust embedded interface.
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Mullarkey Patrick J., Method and apparatus for adjusting data timing by delaying clock signal.
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Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
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Brent Keeth ; Terry R. Lee ; Kevin Ryan ; Troy A. Manning, Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
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Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
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Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
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Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
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Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
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Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
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Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.
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Troy A. Manning, Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.
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Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
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Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
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Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
상세보기
Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
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Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
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Brent Keeth, Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same.
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Manning Troy A., Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device.
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Troy A. Manning, Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same.
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Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
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Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
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Tailliet, Fran?ois, Method and system for the adjustment of an internal timing signal or a corresponding reference in an integrated circuit, and corresponding integrated circuit.
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Janzen, Leel S., Method for generating a clock signal.
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Janzen, Leel S., Method for generating a clock signal.
상세보기
Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.
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Aronson, Lewis B.; Hosking, Lucy G., Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition.
상세보기
Aronson, Lewis B.; Hosking, Lucy G., Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition.
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Aronson, Lewis B.; Hosking, Lucy G., Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition.
상세보기
Rajan, Suresh N., Methods and apparatus of stacking DRAMs.
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Rajan, Suresh N.; Smith, Michael J. S.; Wang, David T, Methods and apparatus of stacking DRAMs.
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Janzen, Leel S., Methods for generating a delayed clock signal.
상세보기
Rajan, Suresh Natarajan; Smith, Michael John, Multi-rank partial width memory modules.
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Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
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Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
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Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
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Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
상세보기
Aronson, Lewis B.; Hosking, Lucy G., Optoelectronic transceiver with multiple flag values for a respective operating condition.
상세보기
Jang, Ji Eun, Output controller with test unit.
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Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Performing error detection on DRAMs.
상세보기
Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Phase adjustment apparatus and method for a memory device signaling system.
상세보기
Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Phase adjustment apparatus and method for a memory device signaling system.
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Kizer,Jade M.; Lau,Benedict C.; Vu,Roxanne T.; Nguyen,Huy M.; Yu,Leung; Chou,Adam Chuen Huei, Phase jumping locked loop circuit.
상세보기
Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Power management of memory circuits by virtual memory simulation.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Power saving system and method for use with a plurality of memory circuits.
상세보기
Ferolito, Philip Arnold; Rosenband, Daniel L.; Wang, David T.; Smith, Michael John Sebastian, Programming of DIMM termination resistance values.
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Thomann, Mark R.; Morzano, Christopher K.; Li, Wen, Read/write timing calibration of a memory array using a row or a redundant row.
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Merritt,Todd A.; Morgan,Donald M., Reduced data line pre-fetch scheme.
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Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Refresh management of memory modules.
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Kim, Kyung-Hoon, Register controlled delay locked loop.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a different number of memory circuit devices.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a refresh operation latency.
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Stark, Donald C., Single-clock, strobeless signaling system.
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Stark, Donald C., Single-clock, strobeless signaling system.
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Stark, Donald C., Single-clock, strobeless signaling system.
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Stark,Donald C., Single-clock, strobeless signaling system.
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Stark,Donald C., Single-clock, strobeless signaling system.
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Stark,Donald C., Single-clock, strobeless signaling system.
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Fjelstad, Joseph C., Stackable low-profile lead frame package.
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Wang, David T.; Rajan, Suresh Natarajan, Stacked DIMM memory interface.
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Harrison Ronnie M., Synchronous clock generator including a delay-locked loop signal loss detector.
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Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.
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Horowitz, Mark A.; Barth, Richard M.; Hampel, Craig E.; Moncayo, Alfredo; Donnelly, Kevin S.; Zerbe, Jared L., System and dynamic random access memory device having a receiver.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits.
상세보기
Merritt, Todd A.; Morgan, Donald M., System and method for implementing data pre-fetch having reduced data lines and/or higher data rates.
상세보기
Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
상세보기
Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
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Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
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Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for power management in memory systems.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
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Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.
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Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.
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Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.
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Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.
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James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
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James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
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James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
상세보기
Rajan, Suresh Natarajan, System including memory stacks.
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Kizer, Jade M.; Lau, Benedict C.; Hampel, Craig E., System with dual rail regulated locked loop.
상세보기
Kizer, Jade M.; Lau, Benedict C.; Vu, Roxanne T.; Hampel, Craig E., System with phase jumping locked loop circuit.
상세보기
Kizer, Jade M.; Lau, Benedict C.; Vu, Roxanne T.; Hampel, Craig E., System with phase jumping locked loop circuit.
상세보기
Hampel, Craig E.; Perego, Richard E.; Sidiropoulos, Stefanos S.; Tsern, Ely K.; Ware, Fredrick A., Timing calibration apparatus and method for a memory device signaling system.
상세보기
Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
상세보기
Wang, David T.; Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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[미국특허] Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 원문보기

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[미국특허] Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 원문보기

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대표청구항 ▼

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