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An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photor

An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

대표청구항 ▼

[ What is claimed is:] [1.] A test structure for the evaluation of gate oxide quality comprising:(a) an array of MOS capacitors formed on a silicon wafer comprising:(i) a gate oxide formed over each of an array of islands of active silicon area surrounded by a field oxide, wherein each of said array

[ What is claimed is:] [1.] A test structure for the evaluation of gate oxide quality comprising:(a) an array of MOS capacitors formed on a silicon wafer comprising:(i) a gate oxide formed over each of an array of islands of active silicon area surrounded by a field oxide, wherein each of said array of islands defines a lower plate of one of said array of MOS capacitors;(ii) an array of polysilicon plates formed over said gate oxides, each of said array of polysilicon plates covering a corresponding gate oxide of one of said array of islands and extending over said field oxide, thereby forming an upper plate of one of said array of MOS capacitors;(b) a dielectric layer over said array of MOS capacitors;(c) a plurality of conductive contacts formed in openings in said dielectric layer, each of said plurality of conductive contacts connected to one of said array of polysilicon plates;(d) a metal stripe patterned over said dielectric layer interconnecting said polysilicon plates through said conductive contacts;(e) a protective diode connected between said metal stripe and said silicon wafer; and(f) a probe pad connected to said metal stripe.