$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Geometry instructions for decompression of three-dimensional graphics data 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
  • G06T-001/20
출원번호 US-0036743 (1998-03-09)
발명자 / 주소
  • Deering Michael F.
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Conley, Rose & Tayon, P.C.Munyon
인용정보 피인용 횟수 : 54  인용 특허 : 27

초록

Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output

대표청구항

[ What is claimed is:] [1.] A method for decompressing a plurality of variable-length instructions, said method comprising:receiving a data stream which includes a first instruction of said plurality of variable-length instructions, wherein said first instruction is executable to perform a first ope

이 특허에 인용된 특허 (27)

  1. Harrell Chandlee Bryant (Mountain View CA), Apparatus for efficiently accessing graphic data for rendering on a display.
  2. Deering Michael F. (Los Altos CA), Command preprocessor for a high performance three dimensional graphics accelerator.
  3. Drucker Steven M. ; Mitchell Donald P., Compression of graphic data normals.
  4. Deering Michael F., Compression of three-dimensional graphics data including quantization, delta-encoding, and variable-length encoding.
  5. Sfarti Adrian ; Baker Nicholas Robert ; Laker Robert William ; Malamy Adam Craig, Controlling a real-time rendering engine using a list-based control mechanism.
  6. Knowles Gregory P. (Palma ESX) Lewis Adrian S. (Palma ESX), Data compression and decompression.
  7. Denenberg Jeffrey N. (345 Putting Green Rd. Trumbull CT 06611) Weinberger Edward D. (370 Central Park West ; Apt. 409 New York NY 10025) Gordon Michael L. (34 Hickory Hill Dr. Dobbs Ferry NY 10522), Data compression method for use in a computerized informational and transactional network.
  8. Heaton Robert J. (San Jose CA), Data compression process.
  9. Mahoney James V. (Sunnyvale CA), Dense aggregative hierarhical techniques for data analysis.
  10. Deering Michael F. (Los Altos CA), Draw processor for a high performance three dimensional graphic accelerator.
  11. Deering Michael F. (Los Altos CA), Floating-point processor for a high performance three dimensional graphics accelerator.
  12. Mahoney James V. (Sunnyvale CA), Hierarchical operations on border attribute data for image regions.
  13. Watanabe Osamu (Tokyo JPX) Komatsu Kosuke (Kanagawa JPX) Ishibashi Masaichi (Saitama JPX) Kimura Mutsumi (Tokyo JPX) Koyama Shinsuke (Tokyo JPX) Fujimori Takahiro (Tokyo JPX) Fujiwara Tadashi (Tokyo , Image forming apparatus and method.
  14. Deering Michael F. ; Wynn Aaron S., Method and apparatus for decompression of compressed geometric three-dimensional graphics data.
  15. Micco Felice A. ; Banton Martin E., Method and apparatus for image rotation with reduced memory using JPEG compression.
  16. Golin Stuart J. (East Windsor NJ) Eggert Jonathan A. (Tigard OR), Method and apparatus for simulating movement in multidimensional space with polygonal projections.
  17. Saini Avtar (San Jose CA), Method and circuitry for performing multiple stack operations in succession in a pipelined digital computer.
  18. Sayah John Y. (Fishkill NY) Rozwod Robert A. (Hopewell Junction NY), Method for restructuring physical design images into hierarchical data models.
  19. Hirai Makoto,JPX, Method of compressing and decoding shape-data.
  20. Chiang Kuang-Wei (Easton PA) Lo Chi-Yuan (Basking Ridge NJ) Paik Doowan (Scotch Plains NJ) Su Shun-Lin (Macungie PA), Method of compressing data for use in performing VLSI mask layout verification.
  21. Sakaibara Toru (Kawasaki JPX) Takamatsu Ryoichi (Hitachi JPX) Hara Hideyuki (Hitachi JPX), Parallel graphics processor with graphics command distributor and command sequencing method.
  22. Reilly Shirley L. (Hillsboro OR), Polygon display apparatus and method.
  23. Newman Steve (1520 Sand Hill Rd. #210 Palo Alto CA 94304), Polygon engine for updating computer graphic display employing compressed bit map data.
  24. Koss Louise A. ; Krech ; Jr. Alan S., Polyline and triangle strip data management techniques for enhancing performance of computer graphics system.
  25. Gertz Jeffrey L. (Marblehead MA) Grappel Robert D. (Concord MA), Storage and transmission of compressed weather maps and the like.
  26. Giokas Dennis G. (8 Kyle Dr. Nashua NH 03062) Desrochers Cynthia A. (40 Sycamore Dr. Leominster MA 01453), System and method for emulating a window management environment having a uniform windowing interface.
  27. Deering Michael F., System and method for transferring compressed three-dimensional graphics data.

이 특허를 인용한 특허 (54)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Foster, Jr.,Steven Gregory; Kong,Thomas H.; Ho,Shaun; Papakipos,Matthew, Apparatus and method for processing dual format floating-point data in a graphics processing system.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Kohli Ashu ; Koob Christopher Edward ; Lanzoni Thomas P. ; Pafumi James Anthony ; Wall William Alan ; Whaley Jeffrey Allan, Computer graphics system with dual FIFO interface.
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  21. Bellamy, Rachel K. E.; Desmond, Michael; Martino, Jacquelyn A.; Matchen, Paul M.; Ossher, Harold L.; Richards, John T.; Swart, Calvin B., Creating tag clouds based on user specified arbitrary shape tags.
  22. Bellamy, Rachel K. E.; Desmond, Michael; Martino, Jacquelyn A.; Matchen, Paul M.; Ossher, Harold L.; Richards, John T.; Swart, Calvin B., Creating tag clouds based on user specified arbitrary shape tags.
  23. Seroussi, Jonathan; Weiss, Tal, Device, system, and method of computer aided design (CAD).
  24. Seroussi, Jonathan; Weiss, Tal, Device, system, and method of computer aided design (CAD).
  25. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  26. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  27. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  28. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  29. Mittal,Millind; Kharidia,Mehul; Tripathy,Tarun Kumar; Mertoguno,J. Sukarno, Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests.
  30. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  32. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  33. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  34. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  35. Lin, Shuaibin, Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions.
  36. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  37. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  38. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  39. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  40. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  43. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  46. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  47. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  48. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  49. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  50. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  51. Master,Paul L.; Watson,John, Storage and delivery of device features.
  52. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  53. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  54. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로