초록 ▼

According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC

According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.

대표청구항 ▼

[ I claim:] [1.] A circuit for setting the logic level of a node, the circuit comprising:a latch circuit having an output, the latch circuit configured to power up with said output at a first state;said latch circuit output coupled to said node and driving said node to a first logic level when said

[ I claim:] [1.] A circuit for setting the logic level of a node, the circuit comprising:a latch circuit having an output, the latch circuit configured to power up with said output at a first state;said latch circuit output coupled to said node and driving said node to a first logic level when said latch circuit output is at said first state; andwherein said latch circuit output is switched to a second state when said node is externally driven to a second logic level;the latch circuit comprising:a) an inverter, said inverter having an input and an output;b) a NAND circuit, said NAND circuit having a first input, a second input and a output, said first input connected to the output of said inverter and wherein the output of said NAND circuit is the latch circuit output and is coupled to the inverter input and wherein said the second input of said NAND circuit is coupled to the node; andc) a level setting transistor having a gate and a drain, wherein said gate is tied to the output of said NAND circuit and wherein said drain is tied to said node and to the second input of said NAND circuit.