초록 ▼

This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture

This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

대표청구항 ▼

[ We claim:] [1.] A method of formatting images comprising frames of video data comprising the steps of:receiving video data as tokens having a frame rate and an arrival rate;defining at least three buffers for storage of the data, one of said buffers being a display buffer, and another of said buff

[ We claim:] [1.] A method of formatting images comprising frames of video data comprising the steps of:receiving video data as tokens having a frame rate and an arrival rate;defining at least three buffers for storage of the data, one of said buffers being a display buffer, and another of said buffers being an arrival buffer;generating write addresses for storing data in said buffers;generating read addresses for reading data stored in said buffers;responsive to said step of generating read addresses, displaying data from said display buffer at a display rate; andresponsive to said arrival rate, said display rate, and said frame rate, allocating said buffers to accommodate said steps of generating write addresses and generating read addresses;defining a plurality of 2-wire interfaces each comprising: a sender, a receiver, and a clock connected to said sender and said receiver, said clock having transitions from a first state to a second state, wherein data is transferred from said sender to said receiver upon a clock transition only when said sender is ready and said receiver is ready;providing control signals for controlling said steps of generating write addresses, generating read addresses, and allocating said buffers, wherein said control signals are communicated via said 2-wire interfaces.