초록 ▼

A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying

A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.

대표청구항 ▼

[ What is claimed is:] [1.] A method to prevent copper diffusion into dielectric layers in the fabrication of a damascene via in the manufacture of an integrated circuit device comprising:providing copper traces through an isolation layer overlying a semiconductor substrate;depositing a passivation

[ What is claimed is:] [1.] A method to prevent copper diffusion into dielectric layers in the fabrication of a damascene via in the manufacture of an integrated circuit device comprising:providing copper traces through an isolation layer overlying a semiconductor substrate;depositing a passivation layer overlying said copper traces and said isolation layer;depositing a dielectric layer overlying said passivation layer;depositing a cap layer overlying said dielectric layer;patterning said cap layer and said dielectric layer to form an opening for planned said damascene via and to expose the top surface of said passivation layer overlying said copper traces;depositing a barrier layer overlying said passivation layer and said dielectric layer;etching through said barrier layer to expose the top surfaces of said passivation layer and said cap layer wherein remaining said barrier layer isolates sidewalls of said opening; andetching through said passivation layer to the top surface of said copper traces to complete said damascene via in the manufacture of said integrated circuit device.