초록 ▼

The invention relates to an extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circ

The invention relates to an extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.

대표청구항 ▼

[ What is claimed is:] [1.] An extended dynamic range imager, comprising:(a) an array of pixels for providing an output signal for each pixel related to an amount of light captured for each pixel during an integration period;(b) a row of extended dynamic range (XDR) sample and hold circuits having a

[ What is claimed is:] [1.] An extended dynamic range imager, comprising:(a) an array of pixels for providing an output signal for each pixel related to an amount of light captured for each pixel during an integration period;(b) a row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array for capturing an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period; and(c) a row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array for capturing a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.