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Bottom lead semiconductor chip package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0023287 (1998-02-13)
우선권정보 KR-0008654 (1997-03-14)
발명자 / 주소
  • Chun Heung-Sup,KRX
출원인 / 주소
  • LG Semicon Co., Ltd., KRX
대리인 / 주소
    Fleshner & Kim
인용정보 피인용 횟수 : 176  인용 특허 : 6

초록

A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of

대표청구항

[ What is claimed is:] [1.] A chip package, comprising:a chip;a plurality of lower leads that are attached to a lower side of the chip;a plurality of upper leads that are attached to an upper side of the chip and that are connected to corresponding ones of the lower leads;a plurality of conductive m

이 특허에 인용된 특허 (6)

  1. Song Chi Jung,KRX ; Lee Ju-Hwa,KRX, Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package.
  2. Fujisawa Tetsuya,JPX ; Sato Mitsutaka,JPX ; Kasai Junichi,JPX ; Mizukoshi Masataka,JPX ; Otokita Kosuke,JPX ; Yoshimura Hiroshi,JPX ; Hayashida Katsuhiro,JPX ; Takashima Akira,JPX ; Ishiguri Masahiko, Semiconductor device and semiconductor device unit for a stack arrangement.
  3. Tsubosaki Kunihiro (Hino JPX) Tanimoto Michio (Kokubunji JPX) Nishi Kunihiko (Kokubunji JPX) Ichitani Masahiro (Kodaira JPX) Koike Shunji (Kodaira JPX) Suzuki Kazunari (Tokyo JPX) Kimoto Ryosuke (Tac, Semiconductor device with lead structure within the planar area of the device.
  4. Cha Gi Bon (Euiwang KRX), Semiconductor package for a semiconductor chip having centrally located bottom bond pads.
  5. An Min Cheol,KRX ; Jeong Do Soo,KRX, Stacked chip package device employing a plurality of lead on chip type semiconductor chips.
  6. Jeong Do Soo,KRX ; An Min Cheol,KRX ; Ahn Seung Ho,KRX ; Jeong Hyeon Jo,KRX ; Choi Ki Won,KRX, Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements.

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