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High tensile nitride layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/58
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
출원번호 US-0791867 (1997-01-31)
발명자 / 주소
  • Brigham Lawrence N.
  • Lee Yung-Huei
  • Chau Robert S.
  • Cotner Raymond E.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 27  인용 특허 : 20

초록

An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating

대표청구항

[ What is claimed is:] [1.] An insulating layer in a semiconductor device comprising:a doped oxide layer on a doped region of said semiconductor devices;a nitride film having a residual stress of between -8.times.10.sup.10 dynes/cm.sup.2 and 3.times.10.sup.10 dynes/cm.sup.2 formed on said doped oxid

이 특허에 인용된 특허 (20)

  1. Joshi Rajiv V. (Yorktown Heights NY), Graded oxide/nitride via structure and method of fabrication therefor.
  2. Richman Paul (St. James NY), Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer.
  3. Moslehi Mehrdad M. (Dallas TX), Low-RC multi-level interconnect technology for high-performance integrated circuits.
  4. Ogawa Hisashi (Katano JPX) Naito Yasushi (Toyonaka JPX) Fukumoto Masanori (Osaka JPX), Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact windo.
  5. Madokoro Shoji (Tokyo JPX), Method for forming an electrode layer by a laser flow technique.
  6. Kobayashi Masato (Tokyo JPX) Yamaguchi Yoichi (Tokyo JPX), Method for forming silicon nitride film.
  7. Barber Jeffrey R. (Pittsburgh PA) Breiten Charles P. (Manassass VA) Stanasolovich David (Manassas VA) Theisen Jacob F. (Manassas VA), Method for making borderless contacts.
  8. Thakur Randhir P. S. (Boise ID), Method for optimizing thermal budgets in fabricating semconductors.
  9. Thakur Randir P. S. (Boise ID) Gonzalez Fernando (Boise ID), Method for optimizing thermal budgets in fabricating semiconductors.
  10. Bryant Frank R. (Denton TX) Waters John L. (Carrollton TX), Method of forming tunneling diffusion barrier for local interconnect and polysilicon high impedance device.
  11. Gargini Paolo (Palo Alto CA) Beinglass Israel (Santa Clara CA) Ahlquist Norman (Menlo Park CA), Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate.
  12. Yau Leopoldo D. (Portland OR) Chen Shih-ou (Fremont CA) Lin Yih S. (Beaverton OR), Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition.
  13. Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI) Tarhay Leo (Sanford MI), Multilayer ceramics from silicate esters.
  14. Yokoi Katsuyuki (Shizuoka JPX) Suga Shigeru (Shizuoka JPX) Fujioka Toshio (Shizuoka JPX), Plasma vapor deposition of an improved passivation film using electron cyclotron resonance.
  15. Yoo Chue-San (Hsin-Chuang ; Taipei TWX), Polycide gate MOSFET process for integrated circuits.
  16. Raby Joseph S. (W. Melbourne FL), Process using tungsten for multilevel metallization.
  17. Wei Che-Chia (Plano TX) Tang Thomas E. (Dallas TX) Bohlman James G. (Forney TX) Douglas Monte A. (Coppell TX), Selective silicidation process using a titanium nitride protective layer.
  18. Kyuragi, Hakaru; Oikawa, Hideo, Semiconductor device and process for manufacturing the same.
  19. Watanabe Tohru (Yokohama JPX) Okumura Katsuya (Yokohama JPX), Semiconductor substrate surface processing method using combustion flame.
  20. Chen Fusen (Dallas TX) Bryant Frank R. (Denton TX) Dixit Girish (Dallas TX), Structure and method for contacts in CMOS devices.

이 특허를 인용한 특허 (27)

  1. Armstrong, Mark; Schrom, Gerhard; Tyagi, Sunit; Packan, Paul A.; Kuhn, Kelin J.; Thompson, Scott, CMOS fabrication process utilizing special transistor orientation.
  2. Armstrong,Mark; Schrom,Gerhard; Tyagi,Sunit; Packan,Paul A.; Kuhn,Kelin J.; Thompson,Scott, CMOS fabrication process utilizing special transistor orientation.
  3. Shimizu,Akihiro; Ooki,Nagatoshi; Nonaka,Yusuke; Ichinose,Katsuhiko, CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress.
  4. Li, Zhuang; Rossman, Kent; Yiin, Tzuyuan, Deposition of amorphous silicon films by high density plasma HDP-CVD at low temperatures.
  5. Sudo, Gaku, Dual stress liner device and method.
  6. Sudo, Gaku, Dual stress liner device and method.
  7. Kim, Junjung; Park, Jae eun; Ku, Ja hum; Yang, Daewon, HDP/PECVD methods of fabricating stress nitride structures for field effect transistors.
  8. Chen, Chia-Chung; Huang, Chi-Feng; Lu, Tse-Hua, HVMOS reliability evaluation using bulk resistances as indices.
  9. Huang, Chi-Feng; Chen, Chia-Chung; Lu, Tse-Hua, HVMOS reliability evaluation using bulk resistances as indices.
  10. Chakravarti,Ashima B.; Narasimha,Shreesh; Chan,Victor; Holt,Judson; Chakravarti,Satya N., Material for contact etch layer to enhance device performance.
  11. Zhu, Huilong; Zhong, Huicai; Leobandung, Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  12. Zhu,Huilong; Zhong,Huicai; Leobandung,Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  13. Dyer,Thomas W.; Yang,Haining, Method for forming self-aligned, dual silicon nitride liner for CMOS devices.
  14. Weimer,Ronald A.; DeBoer,Scott J.; Gealy,Dan; Al Shareef,Husam N., Method of processing a transistor gate dielectric film with stem.
  15. Kavalieros, Jack T.; Brask, Justin K.; Datta, Suman; Doyle, Brian S.; Chau, Robert S., Multigate device with recessed strain regions.
  16. Eitan, Boaz, NROM fabrication method.
  17. Eitan, Boaz, NROM fabrication method.
  18. Shimizu, Akihiro; Ooki, Nagatoshi; Nonaka, Yusuke; Ichinose, Katsuhiko, P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode.
  19. Varadarajan,Bhadri N.; Sims,James S.; Singhal,Akhil, PMOS transistor with compressive dielectric capping layer.
  20. Shimizu, Akihiro; Ooki, Nagatoshi; Nonaka, Yusuke; Ichinose, Katsuhiko, Semiconductor device and a method of manufacturing the same.
  21. Yu, Ji Hwan, Semiconductor device and method for fabricating the same.
  22. Shimizu, Akihiro; Ooki, Nagatoshi; Nonaka, Yusuke; Ichinose, Katsuhiko, Semiconductor device including a film for applying stress to a channel formation region to increase current flow.
  23. Shimizu, Akihiro; Ooki, Nagatoshi; Nonaka, Yusuke; Ichinose, Katsuhiko, Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor.
  24. Shimizu,Akihiro; Ooki,Nagatoshi; Nonaka,Yusuke; Ichinose,Katsuhiko, Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same.
  25. Huang,Chien Chao; Chung,Tone Xuan; Yang,Fu Liang, Slim spacer device and manufacturing method.
  26. Shimizu,Akihiro; Ooki,Nagatoshi; Nonaka,Yusuke; Ichinose,Katsuhiko, Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance.
  27. Zhu,Huilong; Tessier,Brian L.; Zhong,Huicai; Li,Ying, Undercut and residual spacer prevention for dual stressed layers.
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