$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Electropolishing copper film to enhance CMP throughput 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C25D-005/52
  • C25D-005/48
  • C23C-016/00
  • H01L-021/20
  • H01L-021/302
출원번호 US-0170220 (1998-10-13)
발명자 / 주소
  • Cheung Robin W.
출원인 / 주소
  • Advanced Micro Devices, Inc.
인용정보 피인용 횟수 : 54  인용 특허 : 12

초록

In-laid metal, e.g., copper or copper alloy, contacts and conductive routing patterns are formed in recesses in the surface of a substrate by a damascene-type process, comprising depositing a layer of an electrically conductive material filling the recesses and covering the substrate surface, reduci

대표청구항

[ What is claimed is:] [15.] A method of manufacturing a semiconductor device, the method comprising the sequential steps of:providing a substrate comprising a semiconductor having thereon a dielectric layer with a surface comprising at least one recessed area and at least one non-recessed area;elec

이 특허에 인용된 특허 (12)

  1. Beyer Klaus D. (Poughkeepsie NY) Guthrie William L. (Poughkeepsie NY) Makarewicz Stanley R. (New Windsor NY) Mendel Eric (Poughkeepsie NY) Patrick William J. (Newburgh NY) Perry Kathleen A. (Lagrange, Chem-mech polishing method for producing coplanar metal/insulator films on a substrate.
  2. Orita Masahiro,JPX ; Sakai Hiroyuki,JPX ; Takeuchi Megumi,JPX ; Tanji Hiroaki,JPX, Electro-conductive oxides and electrodes using the same.
  3. Blanding Douglas, Insulating support device for electrical conductor.
  4. Chen Lai-Juh,TWX, Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates.
  5. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
  6. Wu Chen Bau,TWX ; Peng Shie-Sen,TWX, Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the a.
  7. Zhao Bin, Method of making a damascene metallization.
  8. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  9. Hirose Kazuyuki (Tokyo JPX) Kikuta Kuniko (Tokyo JPX), Semiconductor device having fine contact hole with high aspect ratio.
  10. Sekinger Kurt,CHX ; Fuchs Harald,CHX ; Paulet Jean-Fran.cedilla.ois,CHX ; Fuchs Roman,CHX, Structured surface with peak-shaped elements.
  11. Carey David H. (Austin TX) Pietila Douglass A. (Puyallup WA) Sigmond David M. (Austin TX), Trenching techniques for forming channels, vias and components in substrates.
  12. Carey David H. (Austin TX), Trenching techniques for forming vias and channels in multilayer electrical interconnects.

이 특허를 인용한 특허 (54)

  1. Sun,Lizhong; Tsai,Stan; Redeker,Fritz, Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus.
  2. Thomas,Terence M.; So,Joseph K., CMP system for metal deposition.
  3. Chen,Chao Lung; Chen,Kei Wei; Lin,Shih Ho; Wang,Ying Lang; Lin,Yu Ku; Su,Ching Hwanq; Shih,Po Jen; Sung,Shang Chin, Copper plating of semiconductor devices using single intermediate low power immersion step.
  4. Wang,Hung Ming; Basol,Bulent M.; Talieh,Homayoun, Efficient wafer processing technology.
  5. Duboust, Alain; Sun, Lizhong; Liu, Feng Q.; Wang, Yuchun; Wang, Yan; Neo, Siew; Chen, Liang-Yuh, Electrolyte composition and treatment for electrolytic chemical mechanical polishing.
  6. Sun, Lizhong; Liu, Feng Q.; Neo, Siew; Tsai, Stan; Chen, Liang-Yuh, Electrolyte with good planarization capability, high removal rate and smooth surface finish for electrochemically controlled copper CMP.
  7. Sun,Lizhong; Liu,Feng Q.; Neo,Siew; Tsai,Stan; Chen,Liang Yuh, Electrolyte with good planarization capability, high removal rate and smooth surface finish for electrochemically controlled copper CMP.
  8. Mayer Steven T. ; Contolini Robert J., Electroplanarization of large and small damascene features using diffusion barriers and electropolishing.
  9. Yahalom, Joseph; Padhi, Deenesh; Gandikota, Srinivas; Dixit, Girish A., Electropolishing of metallic interconnects.
  10. Yuichi Wada JP; Hiroyuki Yarita JP; Hisashi Aida JP; Naomi Yoshida JP, Film deposition method and apparatus.
  11. Liu,Feng Q.; Chen,Liang Yuh; Tsai,Stan D.; Hu,Yongqi, Full sequence metal and barrier layer electrochemical mechanical processing.
  12. Liu,Feng Q.; Chen,Liang Yuh; Tsai,Stan D.; Hu,Yongqi, Full sequence metal and barrier layer electrochemical mechanical processing.
  13. Wang,Yan; Liu,Feng Q.; Duboust,Alain; Neo,Siew S.; Chen,Liang Yuh; Hu,Yongqi, Hydrogen bubble reduction on the cathode using double-cell designs.
  14. Sasson Somekh ; Debabrata Ghosh ; Bret W. Adams, Integrated electrodeposition and chemical mechanical polishing tool.
  15. Hsu,Wei Yung; Chen,Liang Yuh; Morad,Ratson; Carl,Daniel A.; Somekh,Sasson, Integrated multi-step gap fill and all feature planarization for conductive materials.
  16. Hsu, Wei-Yung; Chen, Liang-Yuh; Morad, Ratson; Carl, Daniel A.; Somekh, Sasson, Method and apparatus for electro-chemical processing.
  17. Lizhong Sun ; Stan D. Tsai ; Fred C. Redeker, Method and apparatus for electrochemical-mechanical planarization.
  18. Sun, Lizhong; Tsai, Stan D.; Redeker, Fred C., Method and apparatus for electrochemical-mechanical planarization.
  19. Mayer, Steven T.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation.
  20. Mayer, Steven T.; Contolini, Robert J.; Broadbent, Eliot K.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation.
  21. Liu,Feng Q.; Du,Tianbao; Duboust,Alain; Hsu,Wei Yung, Method and composition for electrochemical mechanical polishing processing.
  22. Jia,Renhe; Liu,Feng Q.; Tsai,Stan D.; Chen,Liang Yuh, Method and composition for polishing a substrate.
  23. Liu,Feng Q.; Chen,Liang Yuh; Tsai,Stan D.; Duboust,Alain; Neo,Siew S.; Hu,Yongqi; Wang,Yan; Butterfield,Paul D., Method and composition for polishing a substrate.
  24. Liu,Feng Q.; Du,Tianbao; Duboust,Alain; Wang,Yan; Hu,Yongqi; Tsai,Stan D.; Chen,Liang Yuh; Tu,Wen Chiang; Hsu,Wei Yung, Method and composition for polishing a substrate.
  25. Liu,Feng Q.; Tsai,Stan D.; Hu,Yongqi; Neo,Siew S.; Wang,Yan; Duboust,Alain; Chen,Liang Yuh, Method and composition for polishing a substrate.
  26. Liu,Feng Q.; Tsai,Stan D.; Hu,Yongqi; Neo,Siew S.; Wang,Yan; Duboust,Alain; Chen,Liang Yuh, Method and composition for polishing a substrate.
  27. Reid, Jonathan David, Method for electrochemical planarization of metal surfaces.
  28. Mayer,Steven T.; Reid,Jonathan D.; Rea,Mark L.; Emesh,Ismail T.; Meinhold,Henner W.; Drewery,John S., Method for planar electroplating.
  29. Niuya, Takayuki; Ono, Michihiro; Goto, Hideto; Park, Kyungho; Marumo, Yoshinori; Shimizu, Katsusuke, Method of forming a plated layer to a predetermined thickness.
  30. Komai, Naoki; Nogami, Takeshi; Kito, Hideyuki; Taguchi, Mitsuru; Ando, Katsumi, Method of manufacturing a semiconductor device.
  31. Sato, Shuzo; Nogami, Takeshi; Segawa, Yuji, Method of producing metallic film.
  32. Sergey Lopatin ; Richard J. Huang, Method of re-working copper damascene wafers.
  33. Cheng Chung Lin TW; Chen Hua Yu TW; Tsu Shih TW; Weng Chang TW, Method of reducing dishing and erosion using a sacrificial layer.
  34. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  35. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  36. Mayer, Steven T.; Porter, David W., Modulated metal removal using localized wet etching.
  37. Shue Shau-Lin,TWX ; Tsai Ming-Hsing,TWX ; Tsai Wen-Jye,TWX ; Yu Chen-Hua,TWX, Multi-step electrochemical copper deposition process with improved filling capability.
  38. Chen, Liang-Yuh; Hsu, Wei-Yung; Duboust, Alain; Morad, Ratson; Carl, Daniel A., Planarization of substrates using electrochemical mechanical polishing.
  39. Sato,Shuzo; Nogami,Takeshi; Yasuda,Zenya; Ishihara,Masao, Polishing method and electropolishing apparatus.
  40. Wang, Zhihong; Wang, You; Mao, Daxin; Jia, Renhe; Tsai, Stan D.; Hu, Yongqi; Tian, Yuan A.; Chen, Liang Yuh, Process and composition for conductive material removal by electrochemical mechanical polishing.
  41. Mayer, Steven T.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  42. Mayer, Steven T.; Drewery, John; Hill, Richard S.; Archer, Timothy; Kepten, Avishai, Selective electrochemical accelerator removal.
  43. Mayer, Steven T.; Stowell, Marshall R.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  44. Tsai, Shin-Yeu; Lin, Chia-Hui; Chen, Ching-Yu; Peng, Chui-Ya, Semiconductor structures with shallow trench isolations.
  45. Bailey, III,Andrew D.; Ni,Tuqiang, Small volume process chamber with hot inner surfaces.
  46. Bailey, III,Andrew D.; Ravkin,Michael; Korolik,Mikhail; Yadav,Puneet, Stress free etch processing in combination with a dynamic liquid meniscus.
  47. Lubomirsky,Dmitry, Substrate support with fluid retention band.
  48. Bailey, III,Andrew D.; Lohokare,Shrikant P., System and method for stress free conductor removal.
  49. Bailey, III,Andrew D.; Lohokare,Shrikant P., System and method for surface reduction, passivation, corrosion prevention and activation of copper surface.
  50. Lohokare, Shrikant P.; Bailey, III, Andrew D.; Hemker, David; Cook, Joel M., System, method and apparatus for improved global dual-damascene planarization.
  51. Lohokare, Shrikant P.; Bailey, III, Andrew D.; Hemker, David; Cook, Joel M., System, method and apparatus for improved local dual-damascene planarization.
  52. Bailey, III,Andrew D.; Lohokare,Shrikant P.; Howald,Arthur M.; Kim,Yunsang, System, method and apparatus for self-cleaning dry etch.
  53. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
  54. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로