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Semiconductor package with pre-fabricated cover 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/10
  • H01L-023/04
  • H01L-023/12
출원번호 US-0172451 (1998-10-14)
발명자 / 주소
  • Farnworth Warren M.
  • Hembree David R.
  • Gochnour Derek
  • Akram Salman
  • Jacobson John O.
  • Wark James M.
  • Thummel Steven G.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Gratton
인용정보 피인용 횟수 : 59  인용 특허 : 22

초록

A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provide

대표청구항

[ What is claimed is:] [1.] A semiconductor package comprising:a substrate comprising an external contact;a ridge on the substrate comprising a photopatterned resist;a semiconductor die on the substrate in electrical communication with the external contact and encompassed by the ridge;a cover attach

이 특허에 인용된 특허 (22)

  1. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  2. Grabbe Dimitry G. (Middletown PA) Shipe Joanne E. (Harrisburg PA), Flat IC chip connector.
  3. Mouissie Bob (Berlicum NLX), Integrated circuit connector.
  4. Newman Keith G. (Sunnyvale CA), Integrated circuit package lid.
  5. Rai Akiteru (Nara JPX), Method for mounting semiconductor chip on circuit board.
  6. Ross Richard J., Method of assembling integrated circuit package.
  7. Barber Ivor G., Method of flip chip assembly.
  8. Kim Jong Tae,KRX ; Park Chan Ik,KRX, Method of making an assembly package having an air tight cavity and a product made by the method.
  9. Woosley Alan H. (Austin TX) Downey ; Jr. Harold A. (Austin TX) Mace Everitt W. (Hutto TX), Method of packaging a semiconductor device.
  10. Barnes Lawrence C. (Colorado Springs CO) Thornberg Gary R. (Colorado Springs CO), Multi-chip module with multiple compartments.
  11. Bechtel Richard L. (Sunnyvale CA) Thomas Mammen (San Jose CA) Hively James W. (Sunnyvale CA), Package for an integrated circuit structure.
  12. Mahadevan Dave S. (Mesa AZ) Boughter D. Lawrence (Tempe AZ), Package for electrical components having a molded structure with a port extending into the molded structure.
  13. Pasqualoni Anthony M. (Hamden CT) Mahulikar Deepak (Madison CT) Jewell Francis S. (Meriden CT) Hoffman Paul R. (Modesto CA) Brathwaite George (Hayward CA) McNabb Richard (Manteca CA) Ramirez German (, Polymer plug for electronic packages.
  14. Beddingfield Stanley C. ; Higgins ; III Leo M. ; Gentile John C., Process for underfilling a flip-chip semiconductor device.
  15. Czajkowski David ; Eggleston Neil ; Patterson Janet, Radiation shielding of three dimensional multi-chip modules.
  16. Brendecke Walter H. (Phoenix AZ) Schmidt Kenneth H. (Mesa AZ), Resealable multichip module and method therefore.
  17. Wilson Howard P. (Austin TX) Martin Fonzell D. J. (Austin TX), Self-opening vent hole in an overmolded semiconductor device.
  18. Grabbe Dimitry G. (Middletown PA), Semiconductor chip carrier system.
  19. Farnworth Warren M. ; Hembree David R. ; Gochnour Derek ; Akram Salman ; Jacobson John O. ; Wark James M. ; Thummel Steven G., Semiconductor package with pre-fabricated cover and method of fabrication.
  20. Mertol Atila, System and method for forming a grid array device package employing electomagnetic shielding.
  21. Clayton James E. (10605 Marbury Ct. Austin TX 78726-1312), Thin multichip module.
  22. Imai Ryuji,JPX, Wired base plate and package for electronic parts.

이 특허를 인용한 특허 (59)

  1. Shimodaira,Kazuhiko, Apparatus and methods for manufacturing a piezoelectric resonator device.
  2. Alcoe, David J.; Johnson, Eric A.; Reiss, Matthew M.; Woychik, Charles G., Apparatus to reduce thermal fatigue stress on flip chip solder connections.
  3. Jiang, Tongbi; Schrock, Edward, BGA package having substrate with patterned solder mask defining open die attach area.
  4. Van Campenhout Yves,FRX ; Gilet Dominique,FRX ; Legay Thierry,FRX ; Bono Hubert,FRX, CMS coated microelectronic component and its method of manufacture.
  5. Farrell, Brian; Jaynes, Paul; Taylor, Malcolm, Chip package sealing method.
  6. Farrell, Brian; Jaynes, Paul; Taylor, Malcolm, Chip package sealing method.
  7. Weber Patrick O., Chip package with molded underfill.
  8. Weber, Patrick O., Chip package with molded underfill.
  9. Kenny, Thomas W.; Munch, Mark; Zhou, Peng; Shook, James Gill; Goodson, Kenneth; Corbin, Dave; McMaster, Mark; Lovette, James, Cooling systems incorporating heat exchangers and thermoelectric layers.
  10. Ishii, Ikuko; Sakaguchi, Yoshikazu, Device package and device encapsulation method.
  11. Farrell, Brian; Jaynes, Paul; Taylor, Malcolm, Electronic and optoelectronic component packaging technique.
  12. Farrell,Brian; Jaynes,Paul; Taylor,Malcolm, Electronic and optoelectronic component packaging technique.
  13. Moriya,Bunji; Tajima,Seiichi; Kurosawa,Fumikachi; Hayashi,Shinichiro, Electronic device and manufacturing same.
  14. Mitchell, Craig S., Encapsulation of microelectronic assemblies.
  15. Moden,Walter L., Flip-chip adaptor package for bare die.
  16. Moden,Walter L., Flip-chip adaptor package for bare die.
  17. Moden, Walter L., Grid array packages.
  18. Moden, Walter L., Grid array packages and assemblies including the same.
  19. S. James Studebaker, Hermetically sealed integrated circuit package incorporating pressure relief valve for equalizing interior and exterior pressures when placed in spaceborne environment.
  20. Chiu, Wen-Wen, IC chip package.
  21. Chiu, Wen-Wen, IC chip package.
  22. Liang, Steve Xin, In-situ cavity integrated circuit package.
  23. Liang, Steve X., Integrated circuit package including in-situ formed cavity.
  24. Lengyel,John Michael; Holmes,Jonathan Frank, LED light engine for backlighting a liquid crystal display.
  25. Tsai, Chung-Che, Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package.
  26. Takeda, Shigeo; Ishida, Makoto; Terakami, Mitsushi; Yamamori, Shota, Manufacturing method of light emitting devices.
  27. VanNortwick John, Method and system for fabricating semiconductor components.
  28. Gan, Qing; Warren, Robert W.; Lobianco, Anthony J.; Liang, Steve X., Method for fabricating a wafer level package with device wafer and passive component integration.
  29. Yamauchi,Kouichi; Minamio,Masanori; Shimizu,Katsutoshi; Nagata,Haruto, Method for manufacturing solid-state imaging devices.
  30. Tabrizi, Behnam, Method for wafer level packaging of electronic devices.
  31. Datta, Madhav; McMaster, Mark; Brewer, Rick; Zhou, Peng; Tsao, Paul; Upadhaya, Girish; Munch, Mark, Method of fabricating high surface to volume ratio structures and their integration in microheat exchangers for liquid cooling system.
  32. Alcoe, David J.; Johnson, Eric A.; Reiss, Matthew M.; Woychik, Charles G., Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections.
  33. Tashiro, Kazuhiro; Fukuda, Keisuke; Kohashi, Naohito; Maruyama, Shigeyuki, Method of semiconductor device protection.
  34. Tashiro, Kazuhiro; Fukuda, Keisuke; Kohashi, Naohito; Maruyama, Shigeyuki, Method of semiconductor device protection, package of semiconductor device.
  35. Patrick O. Weber, Method of underfilling an integrated circuit chip.
  36. Moden, Walter L., Methods for providing and using grid array packages.
  37. Nilsson, Rolf, Module.
  38. Nilsson, Rolf, Module.
  39. Nilsson, Rolf, Module.
  40. Nilsson, Rolf, Module.
  41. Nilsson, Rolf, Module.
  42. Nilsson, Rolf, Module.
  43. Uchiyama Kenji,JPX, Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment.
  44. Chuang, Jason; Chen, Allis; Hsieh, Jachson; Tu, Hsiu Wen; Tsai, Meng Ru; Ho, Mon Nan; Huang, Fu Yung; Chiu, Yung Sheng; Wu, Jichen; Hsu, Chih Cheng, Package structure for a photosensitive chip.
  45. Chen, Po Hung; Chen, Mao Jung, Packaging method of a light-sensing semiconductor device and packaging structure thereof.
  46. Jang, Jaegwon; Kim, Youngjae; Lee, Baikwoo, Printed circuit board.
  47. Hirokazu Honda JP, Semiconductor device having a flip chip cavity with lower stress and method for forming same.
  48. Chung, Kam Cheong; Zulmuhtasyim, Ahmad; Cheng, Liang Peng; Chan, Lai Theng, Semiconductor device package and method of manufacturing the same.
  49. Tashiro, Kazuhiro; Fukuda, Keisuke; Kohashi, Naohito; Maruyama, Shigeyuki, Semiconductor device packaging structure.
  50. Tashiro,Kazuhiro; Fukuda,Keisuke; Kohashi,Naohito; Maruyama,Shigeyuki, Semiconductor device protection cover, and semiconductor device unit including the cover.
  51. Takasaki, Kosuke; Nishida, Kazuhiro; Yamamoto, Kiyofumi, Solid-state imaging device and method for manufacturing the same.
  52. Minamio,Masanori; Yamauchi,Kouichi, Solid-state imaging device and method for producing the same.
  53. Corisis, David J.; Brooks, Jerry M.; Moden, Walter L., Stackable ball grid array package.
  54. Moden, Walter L., Stackable semiconductor device assemblies.
  55. Maruhashi Kenichi,JPX, Substrate for packing semiconductor device and method for packing a semiconductor device in the substrate.
  56. VanNortwick, John, System for fabricating semiconductor components.
  57. Gan, Qing; Warren, Robert W.; Lobianco, Anthony J.; Liang, Steve X., Wafer level package including a device wafer integrated with a passive component.
  58. Warren, Robert W.; Gan, Gene; LoBianco, Tony, Wafer level package with cavities for active devices.
  59. Tabrizi, Behnam, Wafer level packaging using flip chip mounting.
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