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Impedance control circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/985
출원번호 US-0881939 (1997-06-25)
발명자 / 주소
  • Vishwanthaiah Sai V.
  • Starr Jonathan E.
  • Taylor Alexander D.
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin & Friel LLPTerrille
인용정보 피인용 횟수 : 102  인용 특허 : 18

초록

An impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manu

대표청구항

[ What is claimed is:] [1.] An impedance control apparatus for controlling a driver circuit having an output impedance, the driver circuit including a base bit element and a controllable bit element, the controllable bit element being controllable to adjust the output impedance of the driver circuit

이 특허에 인용된 특허 (18)

  1. Schenck Stephen R. (McKinney TX), Adjustable low noise output circuit.
  2. Cooperman Michael (Framingham MA) Sieber Richard W. (Attleboro MA), Bidirectional digital signal transmission system.
  3. Shu Lee-Lean (Los Altos CA) Knorpp Kurt (San Carlos CA), Binary weighted reference circuit for a variable impedance output buffer.
  4. Walters ; Jr. Donald M. (Austin TX), Bit-line isolated, CMOS sense amplifier.
  5. Mu Albert (Milpitas CA), Clocked sense amplifier with positive source feedback.
  6. Hoshi Katsuji (Tokyo JPX), Data latch circuit with improved data write control function.
  7. Dunlop Alfred E. (Murray Hill NJ) Gabara Thaddeus J. (North Whitehall Township ; Lehigh County PA) Knauer Scott C. (Mountainside NJ), Digitally controlled element sizing.
  8. Watarai Seiichi (Tokyo JPX), Driver for interfacing integrated circuits to transmission lines.
  9. Krenik William R. (Dallas TX) Hsu Wei-Chan (Plano TX), High-speed data latch with zero data hold time.
  10. Golab James S. (Austin TX), Latching sense amplifier.
  11. Arcoleo Mathew R. ; Leong Raymond M. ; Johnson Derek ; Churchill Jonathan F.,GBX, Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory.
  12. Shu Lee-Lean (Milpitas CA) Shyu Tai-Ching (San Jose CA), Midpoint sense amplification scheme for a CMOS DRAM.
  13. Nakao Kenji (Itami JPX), Output circuit having reduced switching noise.
  14. Asano Michio (Tokorozawa JPX) Masaki Akira (Musashino JPX) Ishibashi Kenichi (Kokubunji JPX), Output circuit having transistor monitor for matching output impedance to load impedance.
  15. Lamphier Steven H. (St. Albans VT) Pilo Harold (Underhill VT) Schneiderwind Michael J. (Castlerock CO) Towler Fred J. (Essex Junction VT), Programmable impedance output driver.
  16. Iwata Yoshihisa (Kanagawa JPX), Semiconductor sense amplifier.
  17. Obara Takashi (Tokyo JPX) Kaneko Shouji (Tokyo JPX), Sense amplifier circuit.
  18. Jun Dong-Soo (Taegu KRX), Sense amplifier for high performance dram.

이 특허를 인용한 특허 (102)

  1. Martin, Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.
  2. Martin, Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.
  3. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.
  4. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.
  5. Martin,Chris G., Active termination circuit and method for controlling the impedance of external integrated circuit terminals.
  6. Ruesch,Rodney, Anticipatory programmable interface pre-driver.
  7. Starr Jonathan E., Apparatus for dynamic termination logic signaling.
  8. Golshan, Farideh, Apparatus for on-line circuit debug using JTAG and shadow scan in a microprocessor.
  9. Starr Jonathan E., Apparatus for reducing reflections when using dynamic termination logic signaling.
  10. Khieu,Cong Q.; Gu,Louise, Average code generation circuit.
  11. Wilson, John; Kim, Joong-Ho; Kollipara, Ravindranath; Secker, David; Oh, Kyung Suk, Balanced on-die termination.
  12. Oh, Kyung Suk; Shaeffer, Ian P., Buffered memory module having multi-valued on-die termination.
  13. Best,Scott C.; Wong,Anthony Koon; Leung,David, Calibration methods and circuits for optimized on-die termination.
  14. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits for optimized on-die termination.
  15. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  16. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  17. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  18. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  19. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  20. Nguyen, Huy M.; Gadde, Vijay; Lau, Benedict, Calibration methods and circuits to calibrate drive current and termination impedance.
  21. Yu, Shifeng Jack; Khieu, Cong Q.; Cappellano, Ivana, Cascode stage input/output device.
  22. Tran, Tri K.; Khieu, Cong K., Circuit and method for dynamically controlling the impedance of an input/output driver.
  23. Oh, Kyung Suk; Shaeffer, Ian P., Command-triggered on-die termination.
  24. Nguyen, Huy M., Configurable on-die termination.
  25. Nguyen,Huy, Configurable on-die termination.
  26. Oh, Kyung Suk; Shaeffer, Ian P., Controlling a flash device having time-multiplexed, on-die-terminated signaling interface.
  27. Oh, Kyung Suk; Shaeffer, Ian P., Controlling dynamic selection of on-die termination.
  28. Oh, Kyung Suk; Shaeffer, Ian P., Controlling memory devices that have on-die termination.
  29. Oh, Kyung Suk; Shaeffer, Ian P., Controlling on-die termination in a dynamic random access memory device.
  30. Oh, Kyung Suk; Shaeffer, Ian P., Controlling on-die termination in a nonvolatile memory.
  31. Garrett, Jr.,Billy Wayne; Dillon, legal representative,Nancy David; Ching,Michael Tak Kei; Stonecypher,William F.; Chan,Andy Peng Pui; Griffin,Matthew M.; Dillon,John B., Current control technique.
  32. Broyde, Frederic; Clavelier, Evelyne, Digital method and device for transmission with reduced crosstalk.
  33. Broyde,Frederic; Clavelier,Evelyne, Digital method and device for transmission with reduced crosstalk.
  34. Millar, Bruce, Dynamic impedance control for input/output buffers.
  35. Millar, Bruce, Dynamic impedance control for input/output buffers.
  36. Millar, Bruce, Dynamic impedance control for input/output buffers.
  37. Oh, Kyung Suk; Shaeffer, Ian P., Dynamic on-die termination selection.
  38. Volk, Andrew M.; Morrow, Warren R., Dynamic swing voltage adjustment.
  39. Ang, Michael A.; Taylor, Alexander D.; Starr, Jonathan E.; Vishwanthaiah, Sai V., Dynamic termination logic driver with improved impedance control.
  40. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Dynamic termination logic driver with improved impedance control.
  41. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Dynamic termination logic driver with improved slew rate control.
  42. Lin, Mou C.; Andrews, William; Rahman, Arifur, Electronic circuit with on-chip programmable terminations.
  43. Bhattacharya, Dipankar; Kothandaraman, Makeshwar; Kriz, John C.; Marques, Antonio M.; Morris, Bernard L., Enhanced output impedance compensation.
  44. Ruesch, Rodney, GTL+ driver.
  45. Ruesch, Rodney, GTL+Driver.
  46. Karl Schrodinger DE, High-speed output driver.
  47. Yu, Shifeng Jack; Romano, Fabrizio; Cappellano, Ivana; Khieu, Cong Q., Input/output device having dynamic delay.
  48. Yu,Shifeng Jack; Cappellano, legal representative,Ivana; Khieu,Cong Q.; Romano, deceased,Fabrizio, Input/output device having linearized output response.
  49. Oh, Kyung Suk; Shaeffer, Ian P., Integrated circuit device with dynamically selected on-die termination.
  50. Nguyen, Huy, Integrated circuit with configurable on-die termination.
  51. Nguyen, Huy, Integrated circuit with configurable on-die termination.
  52. Nguyen, Huy, Integrated circuit with configurable on-die termination.
  53. Nguyen, Huy, Integrated circuit with configurable on-die termination.
  54. Nguyen, Huy, Integrated circuit with configurable on-die termination.
  55. Oh,Kyung Suk; Shaeffer,Ian P., Integrated circuit with graduated on-die termination.
  56. Pasqualini,Ronald, Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock.
  57. Oh, Kyung Suk; Shaeffer, Ian P., Memory device with programmed device address and on-die-termination.
  58. Oh, Kyung Suk; Shaeffer, Ian P., Memory-module buffer with on-die termination.
  59. Towler, Fred J.; Wistort, Reid A.; Rotella, Jason, Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM).
  60. Douglas ; III Kenneth R., Method and apparatus for controlling impedance on an input-output node of an integrated circuit.
  61. Subratakumar Mandal ; Mirza Jahan, Method and apparatus for improving the performance of buffers using a translator circuit.
  62. Golshan, Farideh; Vishwanthaiah, Sai, Method and apparatus for testing and debugging a circuit.
  63. Blodgett,Greg A.; Morzano,Christopher K., Method and circuit for off chip driver control, and memory device using same.
  64. Blodgett,Greg A.; Morzano,Christopher K., Method and circuit for off chip driver control, and memory device using same.
  65. Broyde,Frederic; Clavelier,Evelyne, Method and device for transmission with reduced crosstalk.
  66. Broyde,Frederic; Clavelier,Evelyne, Method and device for transmission with reduced crosstalk.
  67. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Method for a dynamic termination logic driver with improved impedance control.
  68. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Method for a dynamic termination logic driver with improved slew rate control.
  69. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Method for an output driver with improved impedance control.
  70. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Method for an output driver with improved slew rate control.
  71. Golshan, Farideh, Method for on-line circuit debug using JTAG and shadow scan in a microprocessor.
  72. Ajit, Janardhanan S., Methods and systems for sensing and compensating for process, voltage, temperature, and load variations.
  73. Ajit, Janardhanan S., Methods and systems for sensing and compensating for process, voltage, temperature, and load variations.
  74. Oh, Kyung Suk; Shaeffer, Ian P., Multi-valued on-die termination.
  75. Oh, Kyung Suk; Shaeffer, Ian P., Nonvolatile memory device with on-die control and data signal termination.
  76. Oh, Kyung Suk; Shaeffer, Ian P., Nonvolatile memory device with time-multiplexed, on-die-terminated signaling interface.
  77. Oh, Kyung Suk; Shaeffer, Ian P., Nonvolatile memory with chip-select/device-address triggered on-die termination.
  78. Oh, Kyung Suk; Shaeffer, Ian P., Nonvolatile memory with command-driven on-die termination.
  79. Oh, Kyung Suk; Shaeffer, Ian P., On-die termination control.
  80. Oh, Kyung Suk; Shaeffer, Ian P., On-die termination control.
  81. Shaeffer, Ian P.; Oh, Kyung S., On-die termination of address and command signals.
  82. Shaeffer, Ian; Oh, Kyung Suk, On-die termination of address and command signals.
  83. Shaeffer, Ian; Oh, Kyung Suk, On-die termination of address and command signals.
  84. Shaeffer, Ian; Oh, Kyung Suk, On-die termination of address and command signals.
  85. Shaeffer, Ian; Oh, Kyung Suk, On-die termination of address and command signals.
  86. Shaeffer, Ian; Oh, Kyung Suk, On-die termination of address and command signals.
  87. Allen,Andrew R.; Arnold,Barry J., Output buffer compensation control.
  88. Yu, Shifeng Jack; Khieu, Cong Q.; Romano, Fabrizio; Cappellano, Ivana, Output driver having dynamic impedance control.
  89. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Output driver with improved impedance control.
  90. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Output driver with improved slew rate control.
  91. Nam-Seog Kim KR; Uk-Rae Cho KR, Programmable impedance control circuit and method thereof.
  92. Kim, Yang Gyun; Baik, Seung Beom; Shin, Young Ho, Semiconductor device with impedance calibration function.
  93. Stark, Donald C., Single-clock, strobeless signaling system.
  94. Janzen,Jeffrey W.; Morzano,Christopher, System and method for mode register control of data bus operating mode and impedance.
  95. Janzen,Jeffrey W.; Morzano,Christopher, System and method for mode register control of data bus operating mode and impedance.
  96. Martinez,Boris N., Systems and methods for adjusting an output driver.
  97. Nguyen,Huy M., Systems and methods for controlling termination resistance values for a plurality of communication channels.
  98. Kok, Yew Fatt; Lim, Chooi Pei; Choe, Kok Heng, Techniques for precision biasing output driver for a calibrated on-chip termination circuit.
  99. Starr Jonathan E., Terminating transmission lines using on-chip terminator circuitry.
  100. Starr Jonathan E., Termination of transmission lines using simultaneously enabled pull-up and pull-down circuits.
  101. Khieu,Cong Q.; Gu,Louise, Variably controlled delay line for read data capture timing window.
  102. Huber,Brian W., Voltage regulator and data path for a memory device.

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